NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 36

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
3.2.1.2
36
Figure 9. Clock/Data relationships: Transparent Operating Mode (#0), Sign First, Not
Figure 10. Clock/Data relationships: Transparent Operating Mode (#1), Magnitude First, Not
When the internal scrambler is disabled, the incoming data must be aligned with the quat clock.
The data may be aligned with either the sign bit or the magnitude bit first. If the scrambler is
disabled the user must assure that the 2B1Q pulses are properly scrambled to meet the system PSD
and performance requirements. In Transparent operating Mode with the scrambler disabled the
EMDP could be compatible with other vendor framers while transporting data. In addition, the
EDSP uses internal signals during the activation process to ensure easy and reliable activation. The
transmit and receive data signals share common bit clocks and baud clocks in Transparent
operating Mode.
in Transparent operating Mode.
Scrambled
Scrambled
Independent Operating Modes (4:5)
The Independent operating modes provided by the EMDP use separate transmit and receive clocks
to minimize data transport delay (latency) and to provide constant data delay within the EMDP. In
a transmission system delay occurs in the transmitter, the transport media and the receiver. The
EMDP has small and constant delay in the transmitter and receiver by design. The medium
dependent delay changes linearly with the length of the twisted pair wire. In Transparent operating
mode there is an additional receiver delay required to align the received signal with the BIT_CLK
at the data I/F. The magnitude of this delay is variable, ranging from 0 to a full baud period.
Independent mode removes this delay by providing separate transmit and receive clocks so that the
received data can be output as soon as it is available.
•
•
The internal scrambler disabled, magnitude bit transmitted first (mode #1).
The internal scrambler enabled, sign bit transmitted first (mode #2).
QUAT_CLK
QUAT_CLK
BIT_CLK
BIT_CLK
RDATA
RDATA
TDATA
TDATA
Figure
9,
Magnitude r
Magnitude t
Figure 10
Sign r
Sign t
and
Magnitude r
Magnitude t
Sign t
Sign r
Figure 11
Magnitude r+1
Magnitude t+1
show the data and clock relationships available
Sign r+1
Sign t+1
Magnitude t+1
Magnitude r+1
Sign r+1
Sign t+1
Magnitude r+2
Magnitude t+2
Sign t+2
Sign r+2
Datasheet