NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 40

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
3.2.2
40
Figure 15. Clock/Data Relationships: Framed Mode (#7), Scrambled (4702/4706 bits per frame)
B) Transmit Timing–With Stuff Bits
RDATA_ST
RDATA_ST
A) Transmit Timing–Without Stuff Bits
D) Receive Timing–With Stuff Bits
C) Receive Timing–Without Stuff Bits
BIT_CK
TDATA
BIT_CK
BIT_CK
RDATA
RDATA
BIT_CK
TDATA
TFP
RFP
RFP
TFP
Timing and Data Synchronization
The EMDP implements a synchronous, echo-cancelled communications system. For such a system
to work properly, both Data Pumps must share a common clock. This common system clock is
generated at the Master and sent over the data link to the Slave Data Pump.
MDSL link between a Master and Slave transceiver. This figure illustrates the clock/timing
architecture of the Data Pump in both modes. Link activation is initiated by the Master mode
device which also operates as the MDSL timing source. The Slave mode device recovers the
MDSL clock from the received data and uses this clock to transmit data towards the Master.
b1-b14 are the frame sync word generated by the EDSP (not sampled from TDATA)
b4703-b14 are the stuff bits and frame sync word generated by the EDSP (not sampled from TDATA)
b4699
b4703
b4701
b4702
b4700
b4704
b4702
b4703
b4701
b4705
b4704
b4705
b4702
b4706
b4706
b1
b1
b2
b2
b3
b3
b4
b4
b5
b5
b6
b6
b7
b7
b8
b8
b9 b10 b11
b9 b10 b11
b12 b13 b14 b15
b12 b13 b14 b15
b15 b16
Figure 16
shows an
Datasheet
b15 b16