NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 50

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
3.2.5.2
50
ACT Bits
1. S0 = Two level (±3) signal
2. S1 = Four level (±3, ±1) signal
3. See
0100
0101
0000
1000
0000
[3:0]
0011
0110
0111
0111
RD5
Table 23. Details of Activating State (Continued)
Table 22
4LVLDET
Receiver
FRMDET
SIGDET
AAGC
Active
Active
State
PLL
EC
for the source of the S0 and S1 signals. The source of the signals is mode dependent.
Normal Operation
Both Data Pumps should be in the IDLE state prior to the start of an activation sequence.
Activation always begins at the Master with the assertion of ACTREQ. The Master sends the S0
signal, and presets its AGC (pre-AGC sub-state) and Echo-Canceler (EC) (pre-EC sub-state)
circuits based on its own transmitted signal. The Master moves between states based on its MAT.
When the Master timer has passed SMT2, it enters the SIGDET sub-state where it remains until
detection of an S0 signal from the Slave.
If Master and Slave are connected and the Slave is in the Inactive state, the Slave detects the S0
signal from the Master, and starts its MAT. The Slave enters the Wait sub-state, and begins training
its AGC. The Slave does not transmit any signal until MAT exceeds SMT2. At that time, the Slave
transmits an S0 signal and enters the EC sub-state where the Echo canceler and the Digital AGC
are trained.
The Master detects the S0 signal from the Slave, and resets the MAT to SMT2+1. This re-
synchronization process assures that Master and Slave state machines will be synchronized for the
remainder of the activation process. In most activation, attempts where the Slave is connected to
the line and is in the Inactive state at the beginning of the activation attempt, the Slave will begin to
canceler and digital
Trains analog AGC
Waits for receipt of
Waits for receipt of
State Description
phase of received
signal from Slave
signal.Train DFE
2 consecutive
Trains PLL to
Frame Synch
EMDP Master States
Trains echo
Detects S1.
Fully Active
Fully Active
and FFE.
The following states are present only in framed modes 6 and 7
Words
AGC
TDELTA
TDELTA
TDELTA
Ends at
SMT3 +
SMT4 +
SMT5 +
LOS=0
Driven
Driven
Data
Data
Signal
Xmit
S0
S0
S0
S0
S1
S1
S1
4LVLDET
Receiver
FRMDET
Active
Active
State
PLL1
PLL2
EC
EMDP Slave States
Trains echo canceler
Waits for receipt of 2
Trains PLL to phase
Not present in modes 0 - 5
Not present in Slave Mode
Train DFE and FFE
consecutive Frame
State Description
of received signal.
and digital AGC
received signal
Trains PLL to
Synch Words
frequency of
Detects S1.
Fully Active
Fully Active
Ends at
Driven
Driven
SMT3
SMT5
SMT4
Data
Data
Datasheet
Signal
Xmit
S0
S0
S0
S0
S1
S1
S1