KSZ8721SL A4 Micrel Inc, KSZ8721SL A4 Datasheet - Page 30
![no-image](/images/manufacturer_photos/0/4/434/micrel_inc_sml.jpg)
KSZ8721SL A4
Manufacturer Part Number
KSZ8721SL A4
Description
Manufacturer
Micrel Inc
Datasheet
1.KSZ8721SL_A4.pdf
(34 pages)
Specifications of KSZ8721SL A4
Lead Free Status / RoHS Status
Compliant
KS8721BL/SL
Symbol
t
Reset Circuit Diagram
Micrel recommendeds the following discrete reset circuit as shown in Figure 10 when powering up the KS8721BL/SL device.
For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the
reset circuit as shown in Figure 11.
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/
FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO
voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.
M9999-022105
sr
Parameter
Stable Supply Voltages to Reset High
Strap-In
Figure 11. Recommended Circuit for Interfacing with CPU/FPGA Reset
Voltage
RST_N
Supply
Value
KS8721BL/SL
Figure 10. Recommended Reset Circuit.
Table 8. Reset Timing Parameters
RST
KS8721BL/SL
Figure 9. Reset Timing
D1
D1: 1N4148
tsr
RST
10µF
VCC
C
30
D1
R
10k
10µF
VCC
D2
C
D1, D2: 1N4148
R
10k
RST_OUT_n
CPU/FPGA
Min
50
Typ
February 2005
Max
Micrel
Units
µs