TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 47
TXC-06412BIOG
Manufacturer Part Number
TXC-06412BIOG
Description
Manufacturer
Transwitch Corporation
Datasheet
1.TXC-06412BIOG.pdf
(226 pages)
Specifications of TXC-06412BIOG
Lead Free Status / RoHS Status
Not Compliant
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Symbol
MPCLK
MPD15
MPD14
MPD13
MPD12
MPD10
MPD09
MPD08
MPD07
MPD06
MPD05
MPD04
MPD03
MPD02
MPD01
MPD00
MPSEL
MPA13
MPA12
MPA10
MPA09
MPA08
MPA07
MPA06
MPA05
MPA04
MPA03
MPA02
MPA01
MPA00
MPD11
MPA11
MPTS
GENERIC INTEL - HOST PROCESSOR INTERFACE
Lead No.
M1
G4
G3
G2
G1
B1
E4
E3
C2
D2
C1
F4
B2
E2
F3
D1
E1
F2
H4
F1
H3
H2
H1
K4
K3
K2
K1
J4
J3
J2
J1
L4
L3
I/O(T)
I/O/P
I
I
I
I
LVCMOS
LVTTL/
LVTTL PHAST-12P Chip Select (Active Low): This active low
LVTTL Microprocessor Interface Clock: This lead is the clock
LVTTL Address Bus: These leads are the address bus used by
LVTTL Read Strobe (Active low): This active low lead initiates a
- Lead Descriptions -
Type
8mA
sourced by the microprocessor being interfaced to this
device.
Its max. frequency is 50 MHz.
Intel notation: CLK
the host processor for accessing the PHAST-12P for a
read or write cycle.
MPA13 is the most significant bit in the location’s address.
Intel notation: A[ ]
Data Bus: These leads are the bidirectional data bus
used for transferring data between the PHAST-12P and
the host processor.
MPD15 is the most significant bit.
Intel notation: D[ ]
lead enables data transfers between the host processor
and the PHAST-12P through a read or write cycle.
Intel notation: CS
read transfer between the host processor and the
PHAST-12P.
Intel notation: RD
Name/Function
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005
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