XC95144XL-10TQG144I Xilinx Inc, XC95144XL-10TQG144I Datasheet - Page 6

CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP

XC95144XL-10TQG144I

Manufacturer Part Number
XC95144XL-10TQG144I
Description
CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr

Specifications of XC95144XL-10TQG144I

Package
144TQFP
Family Name
XC9500XL
Device System Gates
3200
Maximum Propagation Delay Time
10 ns
Number Of User I/os
117
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
100 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
117
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1375

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC95144XL-10TQG144I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC95144XL-10TQG144I
Manufacturer:
XILINX
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Part Number:
XC95144XL-10TQG144I
Manufacturer:
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Quantity:
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XC95144XL High Performance CPLD
Internal Timing Parameters
6
Symbol
Buffer Delays
Product Term Control Delays
Internal Register and Combinatorial Delays
Feedback Delays
Time Adders
T
T
T
T
T
T
T
T
T
T
T
LOGILP
T
T
T
T
T
T
T
T
ECHO
SLEW
PTCK
PTSR
ECSU
T
PTTS
T
LOGI
GCK
GSR
OUT
T
GTS
COI
AOI
PTA
PDI
SUI
RAI
EN
IN
HI
F
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable
delay
Product term clock delay
Product term set/reset delay
Product term 3-state delay
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
Internal low power logic delay
Fast CONNECT II feedback delay
Incremental product term allocator delay
Slew-rate limited delay
Parameter
www.xilinx.com
XC95144XL-5
Min
2.3
1.4
2.3
1.4
5.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
1.5
1.1
2.0
4.0
2.0
1.6
1.0
5.5
0.5
0.4
6.0
1.0
5.0
1.9
0.7
3.0
0
-
-
-
-
XC95144XL-7
Min
2.6
2.2
2.6
2.2
7.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
2.3
1.5
3.1
5.0
2.5
2.4
1.4
7.2
1.3
0.5
1.4
6.4
3.5
0.8
4.0
6.4
0
-
-
-
-
XC95144XL-10
10.0
Min
3.0
3.5
3.0
3.5
DS056 (v2.0) April 3, 2007
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Product Specification
Max
3.5
1.8
4.5
7.0
3.0
2.7
1.8
7.5
1.7
1.0
7.0
1.8
7.3
4.2
1.0
4.5
0
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R

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