PIC16F1518T-I/SS Microchip Technology, PIC16F1518T-I/SS Datasheet - Page 228
PIC16F1518T-I/SS
Manufacturer Part Number
PIC16F1518T-I/SS
Description
28-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 2.3V-5.5V 2
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1516-EMV.pdf
(344 pages)
Specifications of PIC16F1518T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
28KB (16K x 14)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1518T-I/SS
Manufacturer:
MICROCHIP
Quantity:
1 001
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PIC16(L)F1516/7/8/9
21.6.13.2
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and counts
down to zero. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
FIGURE 21-36:
FIGURE 21-37:
DS41452B-page 228
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
SDA
SCL
BCLIF
RSEN
S
SSPIF
SDA
SCL
RSEN
BCLIF
S
SSPIF
Bus Collision During a Repeated
Start Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
Preliminary
T
BRG
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’,
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
Figure
21-36.
T
Cleared by software
2011 Microchip Technology Inc.
BRG
Interrupt cleared
by software
’0’
’0’
’0’
Figure
21-35).
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