PIC18F26J13-I/SP Microchip Technology, PIC18F26J13-I/SP Datasheet - Page 29
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PIC18F26J13-I/SP
Manufacturer Part Number
PIC18F26J13-I/SP
Description
28-pin, GP, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SPDIP .300
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F26J13-ISS.pdf
(496 pages)
2.PIC18F26J13-ISS.pdf
(558 pages)
3.PIC18F26J13-ISS.pdf
(12 pages)
Specifications of PIC18F26J13-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 29 of 496
- Download datasheet (5Mb)
2.2
The OSCCON, OSCCON2 and OSCTUNE registers
(Register 2-1
of the device clock’s operation, both in full-power
operation and in power-managed modes.
• Main System Clock Selection (SCS)
• Primary Oscillator Circuit Shutdown (PRISD)
• Secondary Oscillator Enable (SOSCGO)
• Primary Clock Frequency 4x multiplier (PLLEN)
• Internal Frequency selection bits (IRCF, INTSRC)
• Clock Status bits (OSTS, HFIOFS, MFIOFS,
• Power management selection (IDLEN)
2.2.1
The System Clock Select bits, SCS<1:0>, select the
main clock source. The available clock sources are
• Primary clock defined by the FOSC<3:0> bits of
• Secondary clock (secondary oscillator)
• Internal oscillator block (HFINTOSC, MFINTOSC
The clock source changes immediately after one or
more of the bits is written to, following a brief clock
transition interval. The SCS bits are cleared to select
the primary clock on all forms of Reset.
2.2.2
The
(IRCF<2:0>) select the frequency output of the internal
oscillator block. The choices are the LFINTOSC source
(31.25 kHz), the MFINTOSC source (31.25 kHz,
250 kHz or 500 kHz) and the HFINTOSC source
(16 MHz) or one of the frequencies derived from the
HFINTOSC postscaler (31.25 kHz to 8 MHz). If the
internal oscillator block is supplying the main clock,
changing the states of these bits will have an immedi-
ate change on the internal oscillator’s output. On
device Resets, the output frequency of the internal
oscillator is set to the default frequency of 1 MHz.
2010 Microchip Technology Inc.
LFIOFS. SOSCRUN, PLLRDY)
CONFIG1H. The primary clock can be the primary
oscillator, an external clock, or the internal
oscillator block.
and LFINTOSC).
Internal
Oscillator Control
MAIN SYSTEM CLOCK SELECTION
INTERNAL FREQUENCY
SELECTION
to
Register
Oscillator
2-3) control several aspects
Frequency
Select
Preliminary
bits
2.2.3
When a nominal output frequency of 31.25 kHz is
selected (IRCF<2:0> = 000), users may choose
which internal oscillator acts as the source. This is
done with the INTSRC bit of the OSCTUNE register
and MFIOSEL bit of the OSCCON2 register. See
Figure 2-2
selection. This option allows users to select a
31.25 kHz clock (MFINTOSC or HFINTOSC) that can
be tuned using the TUN<5:0> bits in OSCTUNE
register, while maintaining power savings with a very
low clock speed. LFINTOSC always remains the
clock source for features such as the Watchdog
Timer and the Fail-Safe Clock Monitor, regardless of
the setting of INTSRC and MFIOSEL bits
This option allows users to select the tunable and more
precise HFINTOSC as a clock source, while
maintaining power savings with a very low clock speed.
2.2.4
The IDLEN bit of the OSCCON register determines
whether the device goes into Sleep mode or one of the
Idle modes when the SLEEP instruction is executed.
PIC18(L)F2X/4XK22
LOW FREQUENCY SELECTION
and
POWER MANAGEMENT
Register 2-1
for specific 31.25 kHz
DS41412D-page 29
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