PIC18LF26J53-I/SP Microchip Technology, PIC18LF26J53-I/SP Datasheet - Page 302
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PIC18LF26J53-I/SP
Manufacturer Part Number
PIC18LF26J53-I/SP
Description
28-pin, USB, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F26J13-ISS.pdf
(496 pages)
2.PIC18F26J53-ISS.pdf
(586 pages)
3.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18LF26J53-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (6Mb)
PIC18F47J53 FAMILY
20.4
The SPI DMA module contains control logic to allow the
MSSP2 module to perform SPI direct memory access
transfers. This enables the module to quickly transmit
or receive large amounts of data with relatively little
CPU intervention. When the SPI DMA module is used,
MSSP2 can directly read and write to general purpose
SRAM. When the SPI DMA module is not enabled,
MSSP2 functions normally, but without DMA capability.
The SPI DMA module is composed of control logic, a
Destination Receive Address Pointer, a Transmit
Source Address Pointer, an interrupt manager and a
Byte Count register for setting the size of each DMA
transfer. The DMA module may be used with all SPI
Master and Slave modes, and supports both
half-duplex and full-duplex transfers.
20.4.1
When enabled, the SPI DMA module uses the MSSP2
module. All SPI input and output signals, related to
MSSP2, are routed through the Peripheral Pin Select
module. The appropriate initialization procedure, as
described in Section 20.4.6 “Using the SPI DMA
Module”, will need to be followed prior to using the SPI
DMA module. The output pins assigned to the SDO2
and SCK2 functions can optionally be configured as
open-drain outputs, such as for level shifting operations
mentioned in the same section.
20.4.2
Although the SPI DMA module is primarily intended to
be used for SPI communication purposes, the module
can also be used to perform RAM to RAM copy opera-
tions. To do this, configure the module for Full-Duplex
Master mode operation, but assign the SDO2 output
and SDI2 input functions onto the same RPn pin in the
PPS module. Also assign SCK2 out and SCK2 in onto
the same RPn pin (a different pin than used for SDO2
and SDI2). This will allow the module to operate in
Loopback mode, providing RAM copy capability.
DS39964B-page 302
SPI DMA
I/O PIN CONSIDERATIONS
RAM TO RAM COPY OPERATIONS
MODULE
Preliminary
20.4.3
The SPI DMA module remains fully functional when the
microcontroller is in Idle mode.
During normal Sleep, the SPI DMA module is not func-
tional and should not be used. To avoid corrupting a
transfer, user firmware should be careful to make
certain that pending DMA operations are complete by
polling the DMAEN bit in the DMACON1 register prior
to putting the microcontroller into Sleep.
In SPI Slave modes, the MSSP2 module is capable of
transmitting and/or receiving one byte of data while in
Sleep mode. This allows the SSP2IF flag in the PIR3
register to be used as a wake-up source. When the
DMAEN bit is cleared, the SPI DMA module is
effectively disabled, and the MSSP2 module functions
normally, but without DMA capabilities. If the DMAEN
bit is clear prior to entering Sleep, it is still possible to
use the SSP2IF as a wake-up source without any data
loss.
Neither MSSP2 nor the SPI DMA module will provide
any functionality in Deep Sleep. Upon exiting from
Deep Sleep, all of the I/O pins, MSSP2 and SPI DMA
related registers will need to be fully re-initialized
before the SPI DMA module can be used again.
20.4.4
The SPI DMA engine is enabled and controlled by the
following Special Function Registers:
• DMACON1
• TXADDRH
• RXADDRH
• DMABCH
IDLE AND SLEEP
CONSIDERATIONS
REGISTERS
2010 Microchip Technology Inc.
• DMACON2
• TXADDRL
• RXADDRL
• DMABCL
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