PIC24F08KA101T-I/MQ Microchip Technology, PIC24F08KA101T-I/MQ Datasheet - Page 70
PIC24F08KA101T-I/MQ
Manufacturer Part Number
PIC24F08KA101T-I/MQ
Description
8KB Flash, 1KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MA240017.pdf
(254 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F16KA101-ISS.pdf
(18 pages)
Specifications of PIC24F08KA101T-I/MQ
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (2.75K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC24F16KA102 FAMILY
REGISTER 8-2:
DS39927B-page 68
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-4
bit 3
bit 1-0
Note 1:
Note:
U-0
U-0
—
—
2:
See Register 3-2 for the description of this bit, which is not dedicated to interrupt control functions.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
Bit 2 is described in Section 3.0 “CPU”.
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
Unimplemented: Read as ‘0’
U-0
U-0
—
—
CORCON: CPU CONTROL REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
Preliminary
(2)
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/C-0, HSC
IPL3
U-0
—
(2)
PSV
R/W-0
U-0
—
(1)
© 2009 Microchip Technology Inc.
x = Bit is unknown
U-0
U-0
—
—
U-0
U-0
—
—
bit 8
bit 0
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