PIC32MX764F128LT-I/PF Microchip Technology, PIC32MX764F128LT-I/PF Datasheet - Page 102
PIC32MX764F128LT-I/PF
Manufacturer Part Number
PIC32MX764F128LT-I/PF
Description
100 PINS, 128KB Flash, 32KB RAM, 80 MHz, USB, CAN, Ethernet, 4 DMA 100 TQFP 14x1
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80IMR.pdf
(254 pages)
Specifications of PIC32MX764F128LT-I/PF
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Processor Series
PIC32MX5x
Core
MIPS32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX764F128LT-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-42:
TABLE 4-43:
Legend:
Legend:
Note
2FF0 DEVCFG3
2FF4 DEVCFG2
2FF8 DEVCFG1
2FFC DEVCFG0
F220
1:
DEVID
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant. Refer to “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80480) for more information.
31:16 FVBUSIO FUSBIDIO
31:16
31:16
31:16
15:0
15:0
15:0
15:0
31:16
15:0
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
DEVICE AND REVISION ID SUMMARY
UPLLEN
31/15
—
—
—
FCKSM<1:0>
31/15
30/14
—
—
—
—
30/14
PWP<3:0>
VER<3:0>
29/13
—
—
—
—
—
FPBDIV<1:0>
29/13
28/12
CP
—
—
—
—
28/12
27/11
—
—
—
—
—
—
—
27/11
OSCIOFNC
(1)
FCANIO
26/10
—
—
—
—
26/10
UPLLIDIV<2:0>
FETHIO
25/9
POSCMOD<1:0>
—
—
—
—
25/9
FMIIEN
24/8
BWP
USERID<15:0>
—
—
—
24/8
DEVID<15:0>
Bits
Bits
FWDTEN
IESO
23/7
—
—
—
—
—
23/7
22/6
22/6
—
—
—
—
—
—
DEVID<27:16>
FPLLMULT<2:0>
FSOSCEN
21/5
—
—
—
—
—
21/5
20/4
20/4
—
—
—
—
—
ICESEL
19/3
19/3
—
—
—
—
WDTPS<4:0>
18/2
18/2
—
PWP<7:4>
FPLLODIV<2:0>
FSRSSEL<2:0>
FPLLIDIV<2:0>
FNOSC<2:0>
17/1
17/1
DEBUG<1:0>
16/0
16/0
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
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