ISP1508BET STEricsson, ISP1508BET Datasheet - Page 17

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ISP1508BET

Manufacturer Part Number
ISP1508BET
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1508BET

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ISP1508BETTM
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NXP Semiconductors
ISP1508A_ISP1508B_2
Product data sheet
8.7.3 SRP charge and discharge resistors
8.10 Power-On Reset (POR)
8.8 Port power control
8.9 Band gap reference voltage
The ISP1508 provides on-chip resistors for short-term charging and discharging of V
These are used by the B-device to request a session, prompting the A-device to restore
the V
previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for
SESS_END to be logic 1. Then the B-device charges V
register bit to logic 1. The A-device sees that V
threshold and starts a session by turning on the V
For an OTG or host application, the ISP1508 uses the PSW_N pin to control the external
power switch for the V
power switch can be connected to the FAULT pin of the ISP1508 to indicate to the ULPI
link the V
When the FAULT pin is not used, connect it to GND.
The band gap circuit provides a stable internal voltage reference to bias the analog
circuitry. This band gap circuit requires an accurate external reference resistor. Connect a
12 k
An internal POR is generated when REG1V8 rises above V
pulse will be generated whenever REG1V8 drops below V
t
To give a better view of the functionality,
internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip
level so that POR pulse is generated to reset all internal circuits. If REG1V8 dips from t2 to
t3 for greater than t
less than t
w(REG1V8_L)
Fig 4.
BUS
1 % resistor between the RREF pin and GND.
power. First, the B-device makes sure that V
BUS
Digital overcurrent detection scheme
w(REG1V8_L)
.
overcurrent status. For the connection scheme, see
w(REG1V8_L)
ISP1508
, the internal POR pulse will not be generated and will remain LOW.
BUS
Rev. 02 — 13 March 2008
5 V supply. The overcurrent detector output of the external
FAULT
PSW_N
V
, another POR pulse is generated. If the dip from t4 to t5 is
BUS
Figure 5
ISP1508A; ISP1508B
BUS
shows a possible curve of REG1V8. The
INDICATOR
BUS
is charged above the session valid
SWITCH
POWER
FAULT
+5 V
WITH
BUS
power.
BUS
ULPI HS USB OTG transceiver
is fully discharged from the
POR(trip)
by setting the CHRG_VBUS
POR(trip)
004aaa864
Figure
for more than
V
. The internal POR
BUS
© NXP B.V. 2008. All rights reserved.
4.
16 of 86
BUS
.

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