ISP1508BET STEricsson, ISP1508BET Datasheet - Page 70

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1508A_ISP1508B_2
Product data sheet
Fig 24. Rise time and fall time
Fig 26. Timing of TX_ENABLE to DP and DM
1.8 V
V
V
V
V
0 V
OH
OH
OL
OL
logic
input
differential
data lines
0.9 V
t
HSR
10 %
, t
FR
t
V
t
PZH
PZL
CRS
, t
LR
90 %
Fig 28. ULPI timing interface
Control OUT
(DIR, NXT)
DATA OUT
Control IN
DATA IN
CLOCK
V
(STP)
(8-bit)
(8-bit)
V
OH
90 %
OL
+ 0.3 V
t
0.3 V
HSF
t
t
PHZ
0.9 V
PLZ
10 %
, t
FF
, t
LF
Rev. 02 — 13 March 2008
004aaa861
t
t
004aaa574
su
su
t
h
t
h
Fig 25. Timing of TX_DAT and TX_SE0 to DP and DM
Fig 27. Timing of DP and DM to RX_RCV, RX_DP and
1.8 V
differential
data lines
V
V
0 V
logic input
OH
OL
logic output
0.8 V
2.0 V
V
V
differential
data lines
OH
OL
RX_DM
0.9 V
ISP1508A; ISP1508B
V
t
CRS
d(o)
t
d(o)
t
PLH(drv)
V
t
t
PLH(se)
PLH(rcv)
CRS
0.9 V
ULPI HS USB OTG transceiver
t
d(o)
© NXP B.V. 2008. All rights reserved.
t
PHL(drv)
0.9 V
t
t
V
PHL(rcv)
PHL(se)
CRS
004aaa993
V
004aaa575
004aaa573
CRS
0.9 V
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