ADV7342BSTZ Analog Devices Inc, ADV7342BSTZ Datasheet - Page 16

• Manufacturer Part Number: ADV7342BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7342BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 11b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7342/ADV7343
P_HSYNC
P_VSYNC
P_BLANK
Y OUTPUT
a = 32 CLOCK CYCLES FOR 525p
a = 24 CLOCK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLOCK CYCLES FOR 525p
b(MIN) = 264 CLOCK CYCLES FOR 625p
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Y7 TO Y0
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMIN
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Y OUTPUT
P_HSYNC
P_BLANK
P_VSYNC
C7 TO C0
Y7 TO Y0
Figure 14. ED-SDR, 16-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
Figure 15. ED-DDR, 8-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
a
a
c
c
Rev. A | Page 16 of 104
b
b
Cb0
Y0
Cb0
Cr0
Y1
Y0
G
Cb2
Y2
Cr0
Cr2
Y3
Y1