ADV7342BSTZ Analog Devices Inc, ADV7342BSTZ Datasheet - Page 3

• Manufacturer Part Number: ADV7342BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7342BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 11b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Copy Generation Management System ........................................ 74
SD Wide Screen Signaling .............................................................. 77
SD Closed Captioning .................................................................... 78
Internal Test Pattern Generation ................................................... 79
SD Timing ........................................................................................ 80
HD Timing ....................................................................................... 85
REVISION HISTORY
3/09—Rev. 0 to Rev. A
Changes to Features Section ............................................................ 1
Deleted Detailed Features Section, Changes to Table 1 ............... 4
Changes to Figure 1 ........................................................................... 5
Changes to Table 6 ............................................................................ 7
Added Digital Input/Output Specifications—1.8 V Section and
Table 7 ................................................................................................. 7
Changes to Digital Timing Specifications—3.3 V Section and
Table 8 ................................................................................................. 8
Added Table 9 .................................................................................... 9
Changes to MPU Port Timing Specifications Section,
Default Conditions .......................................................................... 10
Deleted Figure 20 ............................................................................ 18
Changes to Table 13 ........................................................................ 19
Changes to Table 15 ........................................................................ 20
Changes to MPU Port Description Section ................................. 27
Changes to I
Added Table 16 ................................................................................ 27
Added Figure 49 .............................................................................. 28
Changes to Table 17 ........................................................................ 29
Changes to Table 18 ........................................................................ 29
Changes to Table 21, 0x30 Bit Description .................................. 32
Changes to Table 29 ........................................................................ 39
Changes to Table 30 ........................................................................ 40
Changes to Table 31, 0xA0 Register Name .................................. 42
Changes to Table 32 ........................................................................ 43
Added Table 33 and Table 34 ......................................................... 44
Changes to Standard Definition Only Section ............................ 46
Added Figure 52 .............................................................................. 47
Changes to Figure 53 ...................................................................... 47
Changes to Figure 56, Figure 57, and Figure 58 .......................... 48
SD CGMS ..................................................................................... 74
ED CGMS..................................................................................... 74
HD CGMS .................................................................................... 74
CGMS CRC Functionality ......................................................... 74
SD Test Patterns ........................................................................... 79
ED/HD Test Patterns .................................................................. 79
2
C Operation Section ................................................ 27
Rev. A | Page 3 of 104
Video Output Levels ....................................................................... 86
Video Standards .............................................................................. 90
Configuration Scripts ..................................................................... 92
Outline Dimensions ...................................................................... 104
Renamed Features Section to Design Features Section ............. 50
Changes to ED/HD Nonstandard Timing Mode Section .......... 50
Changes to Figure 60 ...................................................................... 51
Added HD Interlace External P_HSYNC and P_VSYNC
Considerations Section ................................................................... 51
Changes to SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section ................................................... 51
Changes to Programming the F
Changes to Subaddress 0x8C to Subaddress 0x8F Section ........ 53
Changes to Subaddress 0x82, Bit 4 Section ................................. 53
Added SD Manual CSC Matrix Adjust Feature Section ............ 56
Changes to Subaddress 0x9C to Subaddress 0x9F Section ........ 57
Changes to SD Brightness Detect Section ................................... 58
Changes to Figure 71 ...................................................................... 60
Added Sleep Mode Section ............................................................ 68
Changes to Pixel and Control Port Readback Section ............... 68
Added SD Teletext Insertion Section ........................................... 68
Added Unused Pins Section .......................................................... 70
Added Figure 86 and Figure 87 ..................................................... 70
Changes to Power Supply Sequencing Section ........................... 72
Changes to Figure 94 ...................................................................... 75
Changes to SD Wide Screen Signaling Section ........................... 77
Changes to Internal Test Pattern Generation Section ................ 79
Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option
(Subaddress 0x8A = XXXXX000) Section .................................. 80
Added Configuration Scripts Section .......................................... 92
10/06—Revision 0: Initial Version
SD YPrPb Output Levels—SMPTE/EBU N10 ........................ 86
ED/HD YPrPb Output Levels ................................................... 87
SD/ED/HD RGB Output Levels ................................................ 88
SD Output Plots .......................................................................... 89
Standard Definition .................................................................... 92
Enhanced Definition .................................................................. 96
High Definition ........................................................................... 99
Ordering Guide ......................................................................... 104
SC
Section ................................... 53
ADV7342/ADV7343