ADV7342BSTZ Analog Devices Inc, ADV7342BSTZ Datasheet - Page 30

• Manufacturer Part Number: ADV7342BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7342BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 11b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7342/ADV7343
SR7 to
SR0
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
1
2
3
Table 19. Register 0x0A to Register 0x10
SR7 to
SR0
0x0A
x = Logic 0 or Logic 1.
ED = enhanced definition = 525p and 625p.
Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0s84, Bit 6 must also be enabled (SD).
Register
Mode Register 0
ED/HD CSC Matrix 0
ED/HD CSC Matrix 1
ED/HD CSC Matrix 2
ED/HD CSC Matrix 3
ED/HD CSC Matrix 4
ED/HD CSC Matrix 5
ED/HD CSC Matrix 6
Register
DAC 4, DAC 5, DAC 6
output levels
Bit Description
Reserved
HD interlace external
VSYNC
Test pattern black bar.
Manual CSC matrix
adjust
Sync on RGB
RGB/YPrPb output select
SD sync output enable
ED/HD sync output
enable
Bit Description
Positive gain to DAC output voltage
Negative gain to DAC output voltage
and
HSYNC
3
7
0
1
x
x
x
x
x
x
6
0
1
x
x
x
x
x
x
Rev. A | Page 30 of 104
x
5
0
1
x
x
x
x
x
Bit Number
4
0
1
x
x
x
x
x
x
7
0
0
0
…
0
0
1
1
1
…
1
3
0
1
x
x
x
x
x
x
6
0
0
0
…
0
1
1
1
0
…
1
1
2
0
1
x
x
x
x
x
x
5
0
0
0
…
1
0
0
0
0
…
1
x
x
x
x
x
x
1
0
1
x
Bit Number
0
0
x
x
x
x
x
x
x
4
0
0
0
…
1
0
0
0
0
…
1
Register Setting
0 must be written to this bit
Default
If using HD
setting this bit to 1 is recommended (see
the HD Interlace External
P_VSYNC Considerations
information)
Disabled
Enabled
Disable manual CSC matrix adjust
Enable manual CSC matrix adjust
No sync
Sync on all RGB outputs
RGB component outputs
YPrPb component outputs
No sync output
Output SD syncs on HSYNC and VSYNC pins
No sync output
Output ED/HD syncs on HSYNC and
VSYNC pins
LSBs for GY
LSBs for RV
LSBs for BU
LSBs for GV
LSBs for GU
Bits[9:2 ] for GY
Bits[9:2] for GU
Bits[9:2] for GV
Bits[9:2] for BU
Bits[9:2] for RV
3
0
0
0
…
1
0
0
0
0
…
1
2
0
0
0
…
1
0
0
0
0
…
1
HSYNC
1
0
0
1
…
1
0
0
0
1
…
1
0
0
1
0
…
1
0
0
1
0
…
1
/
VSYNC
Register Setting
0%
+0.018%
+0.036%
…
+7.382%
+7.5%
−7.5%
−7.382%
−7.364%
…
−0.018%
P_HSYNC
section for more
interlace mode,
and
Reset
Value
0x20
0x03
0xF0
0x4E
0x0E
0x24
0x92
0x7C
Reset
Value
0x00