ADV7342BSTZ Analog Devices Inc, ADV7342BSTZ Datasheet - Page 48

• Manufacturer Part Number: ADV7342BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7342BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 11b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7342/ADV7343
Whether the ED/HD Y data is clocked in on the rising or falling
edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1]
(see the input sequence shown in Figure 52 and Figure 53).
Figure 56. Simultaneous SD and HD Example Application
Figure 55. Simultaneous SD and ED Example Application
DECODER
DECODER
DECODER
DECODER
SD
HD
SD
HD
1080i
1035i
525p
625p
720p
OR
OR
OR
74.25MHz
74.25MHz
27MHz
YCrCb
CrCb
Y
27MHz
YCrCb
CrCb
Y
8
8
3
2
8
2
8
8
8
3
P_HSYNC,
P_BLANK
P_HSYNC,
P_BLANK
S_VSYNC,
S_HSYNC
CLKIN_A
S[7:0]
C[7:0]
Y[7:0]
P_VSYNC,
CLKIN_B
S_VSYNC,
S_HSYNC
CLKIN_A
S[7:0]
C[7:0]
Y[7:0]
P_VSYNC,
CLKIN_B
ADV7342/
ADV7342/
ADV7343
ADV7343
Rev. A | Page 48 of 104
ENHANCED DEFINITION ONLY (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
Enhanced definition (ED) YCrCb data can be input in an
interleaved 4:2:2 format on an 8-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the P_HSYNC ,
P_VSYNC , and P_BLANK pins.
The interleaved pixel data is input on Pin Y7 to Pin Y0, with
Pin Y0 being the LSB.
CLKIN_A
Y[7:0]
Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV)
Figure 58. ED Only (at 54 MHz) Example Application
INTERLACED TO
PROGRESSIVE
3FF
DECO DER
MPEG2
YCrCb
00
54MHz
YCrCb
00
XY
8
3
Cb0
P_VSYNC,
P_HSYNC,
P_BLANK
CLKIN_A
Y[7:0]
ADV7342/
ADV7343
Y0
Cr0
Y1