ADV7342BSTZ Analog Devices Inc, ADV7342BSTZ Datasheet - Page 96

• Manufacturer Part Number: ADV7342BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7342BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 11b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7342/ADV7343
ENHANCED DEFINITION
Table 86. ED Configuration Scripts
Input Format
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
525p at 59.94 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
625p at 50 Hz
1
Table 87. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 88. 8-Bit 525p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
SDR = single data rate; DDR = dual data rate.
Setting
0x02
0x1C
0x20
0x04
0x01
Setting
0x02
0x1C
0x20
0x00
0x01
Input Data Width
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
8-bit DDR
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p at 59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Pixel data valid.
1
Synchronization Format
EAV/SAV
HSYNC / VSYNC
EAV/SAV
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
Rev. A | Page 96 of 104
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
Table 89. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 90. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x02
0x1C
0x20
0x10
0x04
0x01
0x02
0x1C
0x10
0x04
0x01
Setting
Setting
Output Color Space
YPrPb
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
RGB
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
Table Number
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Table 93
Table 94
Table 95
Table 96
Table 97
Table 98
Table 99
Table 100
Table 101
Table 102
Table 103
Table 104
Table 105
Table 106
Table 107
Table 108
Table 109
Table 110
Table 111