ADV7342BSTZ Analog Devices Inc, ADV7342BSTZ Datasheet - Page 99

• Manufacturer Part Number: ADV7342BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7342BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 11b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Table 110. 24-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
HIGH DEFINITION
Table 112. HD Configuration Scripts
Input Format
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1
SDR = single data rate; DDR = dual data rate.
Setting
0x02
0x1C
0x10
0x10
0x18
0x01
0x28
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
Input Data Width
8-bit DDR
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
8-bit DDR
8-bit DDR
8-bit DDR
8-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
24-bit SDR
1
Synchronization Format
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
Rev. A | Page 99 of 104
Table 111. 24-Bit 625p RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
0x35
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
Setting
0x02
0x1C
0x10
0x10
0x18
0x01
0x28
0x02
Output Color Space
YPrPb
YPrPb
YPrPb
YPrPb
YPrPb
YPrPb
YPrPb
YPrPb
YPrPb
RGB
RGB
YPrPb
RGB
RGB
YPrPb
RGB
RGB
RGB
YPrPb
RGB
RGB
RGB
RGB
RGB
RGB
RGB
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data.
RGB input enabled.
ADV7342/ADV7343
Table Number
Table 113
Table 114
Table 115
Table 116
Table 117
Table 118
Table 119
Table 120
Table 121
Table 122
Table 123
Table 124
Table 125
Table 126
Table 127
Table 128
Table 129
Table 130
Table 131
Table 132
Table 133
Table 134
Table 135
Table 136
Table 137
Table 138