XC5VLX50T-2FFG665C Xilinx Inc, XC5VLX50T-2FFG665C Datasheet - Page 198
XC5VLX50T-2FFG665C
Manufacturer Part Number
XC5VLX50T-2FFG665C
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-2FFG665C
Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-2FFG665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 5: Configurable Logic Blocks (CLBs)
X-Ref Target - Figure 5-23
198
SEL D [1:0], DATA D [3:0]
SEL C [1:0], DATA C [3:0]
SEL B [1:0], DATA B [3:0]
SEL A [1:0], DATA A [3:0]
Fast Lookahead Carry Logic
16:1 Multiplexer
Each slice has an F8MUX. F8MUX combines the outputs of F7AMUX and F7BMUX to form
a combinatorial function up to 27 inputs (or a 16:1 MUX). Only one 16:1 MUX can be
implemented in a slice, as shown in
It is possible to create multiplexers wider than 16:1 across more than one SLICEM.
However, there are no direct connections between slices to form these wide multiplexers.
In addition to function generators, dedicated carry logic is provided to perform fast
arithmetic addition and subtraction in a slice. A Virtex-5 FPGA CLB has two separate carry
chains, as shown in
logic, as shown in
The carry chain in the Virtex-5 device is running upward and has a height of four bits per
slice. For each bit, there is a carry multiplexer (MUXCY) and a dedicated XOR gate for
adding/subtracting the operands with a selected carry bits. The dedicated carry path and
SELF7
SELF7
SELF8
Input
Input
Input
Input
CLK
(D[6:1])
(C[6:1])
(B[6:1])
(A[6:1])
Figure 5-23: 16:1 Multiplexer in a Slice
(CLK)
(CX)
(AX)
(BX)
Figure
6
6
6
6
Figure
A[6:1]
A[6:1]
A[6:1]
A[6:1]
LUT
LUT
LUT
LUT
5-2.
www.xilinx.com
5-1. The carry chains are cascadable to form wider add/subtract
O6
O6
O6
O6
SLICE
Figure
F7BMUX
F7AMUX
5-23.
F8MUX
(Optional)
D Q
(BMUX)
(B)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_5_23_050506
16:1 MUX
Output
Registered
Output
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