LFE2M20E-5F256I LATTICE SEMICONDUCTOR, LFE2M20E-5F256I Datasheet - Page 49
LFE2M20E-5F256I
Manufacturer Part Number
LFE2M20E-5F256I
Description
FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 256-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20E-5F256I
Package
256FBGA
Family Name
LatticeECP2M
Device Logic Units
19000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
140
Ram Bits
1246208
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20E-5F256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
SERDES and PCS (Physical Coding Sublayer)
LatticeECP2M devices feature up to 16 channels of embedded SERDES arranged in quads at the corners of the
devices. Figure 2-39 shows the position of the quad blocks in relation to the PFU array for LatticeECP2M70 and
LatticeECP2M100 devices. Table 2-15 shows the location of Quads for all the devices.
Each quad contains four dedicated SERDES (Ch0 to Ch3) for high-speed, full-duplex serial data transfer. Each
quad also has a PCS block that interfaces to the SERDES channels and contains digital logic to support an array of
popular data protocols. PCS also contains logic to the interface to FPGA core.
Figure 2-39. SERDES Quads (LatticeECP2M70/LatticeECP2M100)
Table 2-15. Available SERDES Quads per LatticeECP2M Devices
SERDES Block
A differential receiver receives the serial encoded data stream, equalizes the signal, extracts the buried clock and
de-serializes the data-stream before passing the 8- or 10-bit data to the PCS logic. The transmit channel receives
the parallel (8- or 10-bit) encoded data, serializes the data and transmits the serial bit stream through the differen-
tial buffers. There is a single transmit clock per quad. Figure 2-40 shows a single channel SERDES and its inter-
face to the PCS logic. Each SERDES receiver channel provides a recovered clock to the PCS block and to the
FPGA core logic.
ECP2M100
ECP2M20
ECP2M35
ECP2M50
ECP2M70
Device
Ch 3
Ch 3
ULC SERDES Quad
LLC SERDES Quad
PCS Digital Logic
PCS Digital Logic
Ch 2
Ch 2
URC Quad
Available
Available
Available
Available
Available
Ch 1
Ch 1 Ch 0
Ch 0
ULC Quad
Available
Available
2-46
—
—
—
Ch 3
Ch 3
LatticeECP2/M Family Data Sheet
URC SERDES Quad
LRC SERDES Quad
PCS Digital Logic
PCS Digital Logic
Ch 2
Ch 2
LRC Quad
Available
Available
Available
—
—
Ch 1
Ch 1 Ch 0
Ch 0
LLC Quad
Architecture
Available
Available
—
—
—
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