MT46V64M8TG-6LAT:F Micron Technology Inc, MT46V64M8TG-6LAT:F Datasheet - Page 61
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MT46V64M8TG-6LAT:F
Manufacturer Part Number
MT46V64M8TG-6LAT:F
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V64M8TG-6LATF.pdf
(91 pages)
Specifications of MT46V64M8TG-6LAT:F
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DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 31 on page 66. The BURST TERMINATE latency is equal to the CL, that
is, the BURST TERMINATE command should be issued x cycles after the READ
command where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 32 on page 67. The
t
defined in the section on WRITEs.) A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided that auto precharge was not acti-
vated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 33 on page 68. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until both
and
last data elements.
DQSS (MAX) case has a longer bus idle time. (
t
RP have been met. Part of the row precharge time is hidden during the access of the
61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
512Mb: x4, x8, x16 DDR SDRAM
DQSS [MIN] and
t
DQSS (NOM) case is shown; the
©2000 Micron Technology, Inc. All rights reserved.
t
DQSS [MAX] are
Operations
t
RAS
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