MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 170
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Central Processing Unit
3.9.10.2
The FPECR, SPR 1022, is a supervisor-level internal status and control register used by the user’s
floating-point assist software envelope. It contains four status bits that indicate whether the result of the
operation is tiny and whether any of three source operands are denormalized. In addition, it contains one
control bit to enable or disable SIE mode. This register must not be accessed by user code.
A listing of FPECR bit settings is shown in
3-26
SRESET
SRESET
Bits
1:27
28
29
30
31
0
Field SIE
Field
Addr
Floating-Point Exception Cause Register (FPECR)
MSB
Name
16
DNC
DNB
DNA
0
SIE
Software must insert a sync instruction before reading the FPECR.
TR
—
17
1
Figure 3-18. Floating-Point Exception Cause Register (FPECR)
Synchronized ignore exception mode control bit.
0 Disable SIE mode
1 Enable SIE mode
Reserved
Source operand C denormalized status bit.
0 Source operand C is not denormalized
1 Source operand C is denormalized
Source operand B denormalized status bit.
0 Source operand B is not denormalized
1 Source operand B is denormalized
Source operand A denormalized status bit.
0 Source operand A is not denormalized
1 Source operand A is denormalized
Floating-point tiny result.
0 Floating-point result is not tiny
1 Floating-point result is tiny
18
2
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-16. FPECR Bit Descriptions
20
4
21
5
Table
—
0000_0000_0000_0000
0000_0000_0000_0000
22
6
NOTE
3-16.
SPR 1022
23
7
Description
—
24
8
25
9
10
26
11
27
DNC DNB DNA
12
28
Freescale Semiconductor
13
29
14
30
LSB
TR
15
31
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