MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 631
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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15.5.3
DDRQS assigns QSPI pin as an input or an output regardless of whether the QSPI submodule is enabled
or disabled. All QSPI pins are configured during reset as general-purpose inputs.
This register does not affect SCI operation. The TXD1 and TXD2 remain output pinsdedicated to the SCI
submodules, and the RXD1and RXD2 pins remain input pins dedicated to the SCI submodules.
Freescale Semiconductor
Note: See bit descriptions in
SRESET
Bits
8:15
Field
Addr
0
1
2
3
4
5
6
7
PORTQS Data Direction Register (DDRQS)
MSB
—
0
QPAPCS3
QPAPCS2
QPAPCS1
QPAPCS0
QPAMOSI
QPAMISO
DDRQS
Name
QPAPC
—
—
S3
1
Figure 15-8. PORTQS Pin Assignment Register (PQSPAR)
QPAPC
Table 15-11
S2
Reserved
0 Pin is assigned QGPIO3
1 Pin is assigned PCS3 function
0 Pin is assigned QGPIO2
1 Pin is assigned PCS2 function
0 Pin is assigned QGPIO3
1 Pin is assigned PCS1 function
0 Pin is assigned QGPIO0
1 Pin is assigned PCS0 function
Reserved
0 Pin is assigned QGPIO5
1 Pin is assigned MOSI function
0 Pin is assigned QGPIO4
1 Pin is assigned MISO function
PORSTQS data direction register. See <XrefBlue>Section 15.5.3, “PORTQS Data
Direction Register (DDRQS),” on page 15-13.
2
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-10. PQSPAR Bit Descriptions
QPAPC
S1
3
QPAPC
S0
4
0000_0000_0000_0000
—
5
0x30 5016
QPAMOSI QPAMISO
6
Description
7
8
Queued Serial Multi-Channel Module
9
10
DDRQS*
11
12
13
14
LSB
15
15-13
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