MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 935
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
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The development port provides a full duplex serial interface for communications between the internal
development support logic of the CPU and an external development tool. The development port can
operate in two working modes: the trap enable mode and the debug mode.
The trap enable mode is used in order to shift into the CPU internal development support logic the
following control signals:
In debug mode the development port controls also the debug mode features of the CPU. For more
information
23.3.1
The debug mode of the CPU provides the development system with the following basic functions:
Freescale Semiconductor
1. Instruction trap enable bits, used for on the fly programming of the instruction breakpoint
2. Load/store trap enable bits, used for on the fly programming of the load/store breakpoint
3. Non-maskable breakpoint, used to assert the non-maskable external breakpoint
4. Maskable breakpoint, used to assert the maskable external breakpoint
5. VSYNC, used to assert and negate VSYNC
DSCK
DSDI
Debug Mode Support
Section 23.4, “Development
Figure 23-5. Functional Diagram of MPC561/MPC563 Debug Mode Support
BKPT, TE,
VSYNC
CPU Core
ECR
DER
9
MPC561/MPC563 Reference Manual, Rev. 1.2
Port.”
TECR
Development Port
Development Port
Shift Register
Control Logic
32
35
DPDR
DPIR
32
Internal
Bus
Development
Port
SIU/
EBI
Logic
Support
Development Support
EXT
BUS
VFLS,
DSDO
FRZ
23-21
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