5962-9952201QYA Cypress Semiconductor Corp, 5962-9952201QYA Datasheet - Page 18
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5962-9952201QYA
Manufacturer Part Number
5962-9952201QYA
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.5962-9952201QYA.pdf
(64 pages)
Specifications of 5962-9952201QYA
# Macrocells
128
Number Of Usable Gates
3800
Frequency (max)
83MHz
Propagation Delay Time
15ns
Number Of Logic Blocks/elements
8
# I/os (max)
69
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
84
Package Type
CLCC
Lead Free Status / RoHS Status
Not Compliant
Document #: 38-03007 Rev. *E
Switching Characteristics
Product Term Clocking Parameters
t
t
t
t
t
t
Pipelined Mode Parameters
t
Operating Frequency Parameters
f
f
f
f
Reset/Preset Parameters
t
t
t
t
t
t
User Option Parameters
t
t
t
t
t
t
f
COPT
SPT
HPT
ISPT
IHPT
CO2PT
ICS
MAX1
MAX2
MAX3
MAX4
RW
RR
RO
PW
PR
PO
LP
SLEW
3.3IO
S JTAG
H JTAG
CO JTAG
JTAG
JTAG Timing Parameters
[13]
[13]
[13, 14, 15]
[13, 14, 15]
[13]
[13]
Parameter
[13, 14, 15]
[13, 14, 15]
Product Term Clock or Latch Enable (PTCLK) to Output
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
Register or Latch Data Hold Time
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
Buried Register Used as an Input Register or Latch Data Hold Time
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Input Register Synchronous Clock (CLK
Clock (CLK
Maximum Frequency with Internal Feedback (Lesser of 1/t
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t
1/(t
Maximum Frequency with External Feedback (Lesser of 1/(t
Maximum Frequency in Pipelined Mode (Lesser of 1/(t
or 1/t
Asynchronous Reset Width
Asynchronous Reset Recovery Time
Asynchronous Reset to Output
Asynchronous Preset Width
Asynchronous Preset Recovery Time
Asynchronous Preset to Output
Low Power Adder
Slow Output Slew Rate Adder
3.3V I/O Mode Timing Adder
Set-up Time from TDI and TMS to TCK
Hold Time on TDI and TMS
Falling Edge of TCK to TDO
Maximum JTAG Tap Controller Frequency
S
+ t
SCS
H
), or 1/t
)
[5]
0
, CLK
Over the Operating Range (continued)
CO
1
)
, CLK
[5]
2
, or CLK
[5]
[5]
[5]
[5]
[5]
3
)
[5]
[5]
[5]
0
, CLK
[5]
Description
1
, CLK
[12]
2
, or CLK
CO
+ t
SCS
CO
IS
), 1/t
, 1/(t
3
Ultra37000 CPLD Family
+ t
) to Output Register Synchronous
S
ICS
S
) or 1/(t
+ t
, 1/(t
H
), or 1/t
WL
WL
+ t
+ t
CO
WH
WH
)
WL
[5]
), 1/(t
)
[5]
+ t
IS
WH
Page 18 of 64
+ t
),
IH
),
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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