MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 70

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 27.
Intel NetStructure
Technical Product Specification
70
Flash
LPC
FPGA/CPLD
IPMB L (To AMC)
IPMB C (To RTM)
(redundant)
LPC Flash
®
The high-level architecture of the baseboard management for the MPCBL0050 is
represented in
IPMC Block Diagram
The main processors communicate with the IPMC using the Keyboard Controller Style
(KCS) interface. The EFI BIOS uses the SMS interface for normal communication and
the SMM interface when executing code under Systems Management Mode (SMM). The
base address of the LPC interface for SMS is 0xCA2/CA3 for the SMS and 0xCA8/CAC
for SMM operation. The EFI BIOS is also able to communicate with the IPMC via the
KCS interface for POST error logging purposes, fault resilient purposes and critical
interrupts.
MPCBL0050 Single Board Computer
Memory
mapped
I/O
Private Bus
SMBUS
IPMB
LPC Bus
Flash
ROM
2MB
Figure
27.
Management Controller
SRAM
256KB
Intelligent Platform
(IPMC)
MCH
CPU
ICH
External
Sensors
Temp
Internal
Flash
EEPROM
Serial
IPMB B
IPMB A
2x GbE
MPCBL0050—Hardware Management
LM93 (Heceta 7)
Isolator
Isolator
Order Number: 318146-001
September 2007
Backplane
Interface
Backplane
Base
ports
(P10)