SC16C850LIBS NXP Semiconductors, SC16C850LIBS Datasheet - Page 36

• Manufacturer Part Number: SC16C850LIBS
• Manufacturer: NXP Semiconductors

Specifications of SC16C850LIBS

• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SC16C850L
Product data sheet
7.22 Advanced Feature Control Register 1 (AFCR1)
Table 32.
[1]
Bit
0
7:5
4
3
2
1
It takes 4 XTAL1 clocks to reset the device.
AFCR1[7:5]
Symbol
AFCR1[4]
AFCR1[3]
AFCR1[2]
AFCR1[1]
AFCR1[0]
Advanced Feature Control Register 1 register bits description
All information provided in this document is subject to legal disclaimers.
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 5 — 1 February 2011
Description
reserved
Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.
reserved
RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to
DTR/DSR.
SReset. Software Reset. A write to this bit will reset the UART. Once the
UART is reset this bit is automatically set to 0.
TSR Interrupt. Select TSR interrupt mode
logic 0 = RX input is level-sensitive. If RX pin is LOW, the UART will
not go to sleep. Once the UART is in Sleep mode, it will wake up if RX
pin goes LOW.
logic 1 = RX input is edge-sensitive. UART will go to sleep even if RX
pin is LOW, and will wake up when RX pin toggles.
logic 0 = RTS and CTS signals are used for hardware flow control.
logic 1 = DTR and DSR signals are used for hardware flow control.
RTS and CTS retain their functionality.
logic 0 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level or becomes empty.
logic 1 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level, or becomes empty and the last stop bit has
been shifted out of the Transmit Shift Register.
SC16C850L
[1]
© NXP B.V. 2011. All rights reserved.
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