CY22381FSZC Cypress Semiconductor Corp, CY22381FSZC Datasheet - Page 3

• Manufacturer Part Number: CY22381FSZC
• Description: IC CLOCK GEN PROG 3-PLL 8-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY22381FSZC

• Pll: Yes
• Input: LVTTL, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1918 - KIT DEV FTG PROGRAMMING KIT428-1456 - SOCKET ADAPTER FOR CY22381
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Pinouts
Pin Definitions
Operation
The CY22381 is an upgrade to the existing CY2081. The new
device has a wider frequency range, greater flexibility, improved
performance, and incorporates many features that reduce PLL
sensitivity to external system issues.
The device has three PLLs that allow each output to operate at
an independent frequencies. These three PLLs are completely
programmable.
The CY223811 is the CY22381 with NiPdAu lead finish.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The frequency of PLL1 can optionally
be changed by using the external CMOS general purpose input.
See the following section on “General-Purpose Input” for more
detail.
PLL2 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.
General-Purpose Input
The CY22381 features an output control pin (pin 8) that can be
programmed to control one of four features.
When programmed as a Frequency Select (FS), the input can
select between two arbitrarily programmed frequency settings.
The Frequency Select can change the following; the frequency
Document #: 38-07012 Rev. *H
CLKC
GND
XTALIN
XTALOUT
CLKB
CLKA
V
FS/SUSPEND/
OE/SHUTDOWN
Name
DD
Pin Number
1
3
4
5
6
2
7
8
Configurable clock output C
Reference crystal input or external reference clock input
Reference crystal feedback (float if XTALIN is driven by external reference clock)
Configurable clock output B
Configurable clock output A
Ground
Power supply
General Purpose Input. Can be Frequency Control, Suspend mode control, Output
Enable, or full-chip shutdown.
Description
Figure 1. CY22381, CY223811- 8-pin SOIC
XTALOUT
XTALIN
CLKC
GND
1
2
3
4
8
7
6
5
of PLL1, the output divider of CLKB, and the output divider of
CLKA. Any divider change as a result of switching the FS input
is guaranteed to be glitch free.
The general-purpose input can simultaneously control the
Suspend feature, turning off a set of PLLs and outputs
determined during programming.
When programmed as an Output Enable (OE) the input forces
all outputs to be placed in a three-state condition when LOW.
When programmed as a Shutdown, the input forces a full chip
shutdown mode when LOW.
Crystal Input
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors must not
be used for MPEG, communications, or other applications that
are sensitive to absolute frequency requirements
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375pF for a total crystal load range of 6pF to 30pF.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application requires
a driven input, then XTALOUT must be left floating.
CLKA
CLKB
FS/
V
DD
SUSPEND
/OE/
SHUTDOWN
CY223811
CY22381
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