CY22381FSZC Cypress Semiconductor Corp, CY22381FSZC Datasheet - Page 6

• Manufacturer Part Number: CY22381FSZC
• Description: IC CLOCK GEN PROG 3-PLL 8-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY22381FSZC

• Pll: Yes
• Input: LVTTL, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1918 - KIT DEV FTG PROGRAMMING KIT428-1456 - SOCKET ADAPTER FOR CY22381
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Electrical Characteristics
Switching Characteristics
Switching Waveforms
Notes
Document #: 38-07012 Rev. *H
I
I
1/t
t
t
t
t
t
t
4. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
DD
DDS
2
3
4
5
6
7
Parameter
Parameter
1
Output Frequency
Output Duty Cycle
Rising Edge Slew Rate
Falling Edge Slew Rate
Output Three-state Timing
Clock Jitter
Lock Time
Total Power Supply Current
Total Power Supply Current in
Shutdown Mode
THREE-STATE
OUTPUT
OUTPUTS
Description
[3]
OE
[3, 6]
ALL
Name
[3, 4]
[3, 5]
Figure 2. All Outputs, Duty Cycle and Rise and Fall Time
[3]
[3]
t
[3]
3
Figure 3. Output Three-State Timing
t
5
Clock output limit, Commercial
Clock output limit, Industrial
Duty cycle for outputs, defined as t
Fout < 100 MHz, divider >= 2, measured
at V
Duty cycle for outputs, defined as t
Fout > 100 MHz or divider = 1, measured
at V
Output clock rise time, 20% to 80% of V
Output clock fall time, 20% to 80% of V
Time for output to enter or leave
three-state mode after SHUTDOWN/OE
switches
Peak-to-peak period jitter, CLK outputs
measured at V
PLL Lock Time from Power up
3.3 V Power Supply; 3 outputs at 50 MHz
3.3 V Power Supply; 3 outputs at 166 MHz
Shutdown active
DD
DD
/2
/2
t
2
Conditions
Description
DD
/2
t
1
[1]
t
4
2
2
÷ t
÷ t
DD
DD
1
1
,
,
45%
40%
0.75
0.75
Min
Min
–
–
–
–
–
–
–
–
t
5
Typ.
50%
50%
Typ
150
200
1.4
1.4
1.0
35
70
–
–
5
Max
Max
55%
60%
200
166
300
20
–
–
–
–
–
3
CY223811
CY22381
Unit
MHz
MHz
V/ns
V/ns
Unit
Page 6 of 11
mA
mA
ms
μA
ns
ps
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