IDT5V49EE702NDGI8 IDT, Integrated Device Technology Inc, IDT5V49EE702NDGI8 Datasheet - Page 16

• Manufacturer Part Number: IDT5V49EE702NDGI8
• Description: IC PLL CLK GEN 200MHZ 28VQFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generator, Multiplexerr

Specifications of IDT5V49EE702NDGI8

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL, Crystal
• Output: HCSL, LVCMOS, LVDS, LVPECL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:7
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IDT5V49EE702DLGI8; IDT5V49EE702DLGI8

I
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
2
IDT5V49EE702
EEPROM PROGRAMMABLE CLOCK GENERATOR
t
C Bus AC Characteristics for Fast Mode
t
Symbol
t
HD:START
t
SU:START
t
SU:STOP
SU:DATA
HD:DATA
F
t
t
t
t
HIGH
SCLK
LOW
BUF
OVD
C
t
t
R
F
B
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
of the SCL signal) to bridge the undefined region of the falling edge of SCL.
Serial Clock Frequency (SCL)
Bus free time between STOP and START
Setup Time, START
Hold Time, START
Setup Time, data input (SDA)
Hold Time, data input (SDA)
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCL)
Fall Time, data and clock (SDA, SCL)
HIGH Time, clock (SCL)
LOW Time, clock (SCL)
Setup Time, STOP
Parameter
1
16
20 + 0.1xC
20 + 0.1xC
Min
100
1.3
0.6
0.6
0.6
1.3
0.6
0
0
B
B
Typ
Max
IDT5V49EE702
400
400
300
300
0.9
CLOCK SYNTHESIZER
Unit
kHz
pF
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
µs
REV F 022310
IH
(MIN)