PI6C2510-133ELE Pericom Semiconductor, PI6C2510-133ELE Datasheet - Page 2
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PI6C2510-133ELE
Manufacturer Part Number
PI6C2510-133ELE
Description
IC PLL CLOCK DVR 10OUT 24-TSSOP
Manufacturer
Pericom Semiconductor
Type
PLL Clock Driverr
Datasheet
1.PI6C2510-133ELE.pdf
(4 pages)
Specifications of PI6C2510-133ELE
Pll
Yes with Bypass
Input
CMOS
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
1:10
Differential - Input:output
No/No
Frequency - Max
150MHz
Divider/multiplier
No/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Frequency-max
150MHz
Number Of Elements
1
Pll Input Freq (min)
25MHz
Pll Input Freq (max)
150MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 85C
Package Type
TSSOP
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Pin Count
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PI6C2510-133ELE
Manufacturer:
PER
Quantity:
372
Company:
Part Number:
PI6C2510-133ELE
Manufacturer:
HARRIS
Quantity:
251
Part Number:
PI6C2510-133ELEX
Manufacturer:
PERICOM
Quantity:
20 000
Pin Functions
DC Specifi cations - Absolute maximum ratings over operating free-air temperature range.
Note: Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
Pin
Name
CLK_IN
FB_IN
G
FB_OUT 12
Y[0:9]
AV
AGND
V
GND
Symbol
V
V
V
I
Power
T
Parameter
I
C
C
O
CC
STG
I
O
CC
I
O
I
_DC
_DC
CC
09-0006
Pin
Number
24
13
11
3, 4, 5, 8,
9, 15, 16,
17, 20,
21
23
1
2, 10, 14,
22
6, 7, 18,
19
Parameter
Input voltage range
Output voltage range
DC input voltage
DC output current
Maximum power dissipation at TA = 59˚C in
still airr
Storage temperature
Test Conditions
V
V
V
I
I
O
= V
= V
= V
CC
CC
Type
I
I
I
O
O
Power
Ground
Power
Ground Ground
CC
or GND
or GND; I
or GND
Description
Reference Clock input. CLK_IN allows spread spectrum.
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Output bank enable. When G is LOW, outputs Y[0:9] are disabled to a logic
low state.
When G is HIGH, all outputs Y[0:9] are enabled.
Feedback output. FB_OUT is dedicated for external feedback.
FB_OUT has an embedded series-damping resistor of same value as clock
outputs Y[0:9].
Clock outputs. These outputs provide low-skew copies of CLK_IN.
Each output has an embedded series-damping resistor.
Analog power supply. AVcc can be also used to bupass the PLL for test
purposes. When AVcc is strapped to ground, PLL is bypassed and CLK_IN
bufferef directly to the device outputs.
Analog ground. AGND provides thr ground referencefor the analog cir-
cuitry/
Power Supply
O
= 0
2
Min.
–0.5
–65
VCC
3.6V
3.3V
Clock Driver with 10 Clock Outputs
Low–noise, Phase –Locked Loop
Min
Max.
V
+5.0
100
1.0
160
CC
+ 0.5
Typ
4
6
PI6C2510-133E
Max
10
PS8505B
Units
V
mA
W
°C
Units
uA
pF
11/18/09