KAD5512P-25Q72 Intersil, KAD5512P-25Q72 Datasheet - Page 29
![IC ADC 12BIT 250MSPS SGL 72-QFN](/photos/6/61/66113/kad5512p-25q72_sml.jpg)
KAD5512P-25Q72
Manufacturer Part Number
KAD5512P-25Q72
Description
IC ADC 12BIT 250MSPS SGL 72-QFN
Manufacturer
Intersil
Series
FemtoCharge™r
Datasheet
1.KAD5512P-25Q72.pdf
(36 pages)
Specifications of KAD5512P-25Q72
Number Of Bits
12
Sampling Rate (per Second)
250M
Data Interface
Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
286mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
72-VFQFN Exposed Pad
For Use With
KDC5512EVAL - DAUGHTER CARD FOR KAD5512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KAD5512P-25Q72
Manufacturer:
Intersil
Quantity:
23
NOTE:
15. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal
pull-up.
(Hex)
C6-FF
Addr
C0
C1
C2
C3
C4
C5
user_patt1_msb
user_patt2_msb
user_patt1_lsb
user_patt2_lsb
Parameter
Reserved
Reserved
Name
test_io
29
(MSB)
Bit 7
User Test Mode
B15
B15
B7
B7
01 = Alternate
10 = Reserved
11 = Reserved
00 = Single
[1:0]
Bit 6
B14
B14
B6
B6
TABLE 17. SPI MEMORY MAP (Continued)
Bit 5
B13
B13
B5
B5
KAD5512P
Bit 4
B12
B12
B4
B4
Reserved
Reserved
1 = Midscale Short
4 = Checker Board
2 = +FS Short
3 = -FS Short
5 = Reserved
6 = Reserved
Bit 3
B11
B11
B3
B3
Output Test Mode [3:0]
0 = Off
Bit 2
B10
B10
B2
B2
9-15 = Reserved
Bit 1
8 = User Input
B1
B9
B1
B9
7 = One/Zero
Toggle
Word
(LSB)
Bit 0
B0
B8
B0
B8
(Hex)
Value
Def.
00h
00h
00h
00h
00h
00h
October 1, 2010
Indexed/
Global
FN6807.4
G
G
G
G
G
G