ADC1207S080HW/C1,1 NXP Semiconductors, ADC1207S080HW/C1,1 Datasheet - Page 9
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ADC1207S080HW/C1,1
Manufacturer Part Number
ADC1207S080HW/C1,1
Description
IC ADC 12BIT PAR 80MHZ 48-HTQFP
Manufacturer
NXP Semiconductors
Datasheet
1.ADC1207S080HWC15.pdf
(21 pages)
Specifications of ADC1207S080HW/C1,1
Number Of Bits
12
Sampling Rate (per Second)
80M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
990mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TQFP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935286582118
ADC1207S080HW/C1-T
ADC1207S080HW/C1-T
ADC1207S080HW/C1-T
ADC1207S080HW/C1-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADC1207S080HW/C1,1
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 5.
V
to +85 C; V
V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
ADC1207S080_2
Product data sheet
Symbol
S/N
SFDR
ACPR
IMD2
IMD3
CCA
CCA
The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC levels vary 1:1 with V
b) PECL mode 2: (DC levels vary 1:1 with V
c) PECL mode 3: (DC levels vary 1:1 with V
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has
Guaranteed by design.
The ADC input range can be adjusted with an external reference connected to pin FSIN. This voltage has to be referenced to V
Output data acquisition: the output data is available after the maximum delay of t
The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
The total harmonic distortion is obtained with the addition of the first five harmonics.
The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
Intermodulation measured relative to either tone with analog input frequencies f
amplitude and the total amplitude of both signals provides full-scale to the converter ( 6 dB below full-scale for each input signal). IMD3
is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; IMD2 is the ratio
of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product.
= 4.75 V to 5.25 V; V
= V
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling
takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF
capacitor.
to be connected to the ground.
CCD
Characteristics
i(IN)
Parameter
signal-to-noise ratio
spurious free dynamic
range
adjacent channel power
ratio
second-order
intermodulation
distortion
third-order
intermodulation
distortion
= 5 V, V
V
i(INN)
CCO
= 0.5 dBFS; V
= 3.3 V, T
CCD
…continued
= 4.75 V to 5.25 V; V
amb
Conditions
f
f
f
f
f
f
f
channel spacing;
B = 3.84 MHz
f
f
f
f
f
f
f
f
f
f
f
f
= 25 C and C
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
ref(fs)
1 = 21 MHz;
2 = 22 MHz
1 = 91.5 MHz;
2 = 94.5 MHz
1 = 174 MHz;
2 = 176 MHz
1 = 21 MHz;
2 = 22 MHz
1 = 91.5 MHz;
2 = 93.5 MHz
1 = 174 MHz;
2 = 176 MHz
= 21.4 MHz
= 93 MHz
= 175 MHz
= 21.4 MHz
= 93 MHz
= 175 MHz
= 93 MHz; 5 MHz
CCD
CCD
CCD
= V
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
) CLK and CLKN inputs are at differential PECL levels.
CCA
Rev. 02 — 7 August 2008
CCO
L
1.87 V; V
= 10 pF; unless otherwise specified.
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
I(cm)
[7]
[8]
[8]
Min
-
63
-
-
68
-
-
-
-
-
-
-
-
= V
CCA
i
d(o)
1 and f
1.95 V; typical values measured at
.
Typ
67.4
67.2
66.5
76
78
74
70
i
89
86
83
88
82
83
2. The two input signals have the same
ADC1207S080
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2008. All rights reserved.
amb
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dB
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
= 40 C
CCA.
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