AD9277BSVZ Analog Devices Inc, AD9277BSVZ Datasheet - Page 7
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AD9277BSVZ
Manufacturer Part Number
AD9277BSVZ
Description
IC ADC 14BIT LNA/VGA/AAF 100TQFP
Manufacturer
Analog Devices Inc
Type
Ultrasound Receiversr
Datasheet
1.AD9277BSVZ.pdf
(48 pages)
Specifications of AD9277BSVZ
Resolution (bits)
14 b
Data Interface
Serial, SPI™
Sampling Rate (per Second)
10M ~ 50M
Voltage Supply Source
Analog and Digital
Voltage - Supply
1.8V, 3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Sampling Rate
50MSPS
Input Channel Type
Single Ended
Supply Voltage Range - Digital
1.7V To 1.9V
Supply Current
365mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9277BSVZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f
Table 2.
Parameter
CLOCK INPUTS (CLK+, CLK−)
CW 4LO INPUTS (4LO+, 4LO−)
LOGIC INPUTS (PDWN, STBY, SCLK, RESET)
LOGIC INPUT (CSB)
LOGIC INPUT (SDIO)
LOGIC OUTPUT (SDIO)
DIGITAL OUTPUTS (DOUTx+, DOUTx−), (ANSI-644)
DIGITAL OUTPUTS (DOUTx+, DOUTx−),
LOGIC OUTPUTS (GPO0, GPO1, GPO2, GPO3)
1
2
3
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
Specified for LVDS and LVPECL only.
Specified for 13 SDIO pins sharing the same connection.
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage (I
Logic 0 Voltage (I
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
Logic 0 Voltage (I
1
OH
OL
OL
= 50 μA)
= 50 μA)
= 800 μA)
3
OS
OS
2
2
)
)
OD
OD
)
)
1
1
Full
Full
Full
Full
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Rev. 0 | Page 7 of 48
Min
250
250
1.2
1.2
1.2
0
247
1.125
150
1.10
IN
= 5 MHz, full temperature, unless otherwise noted.
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
Typ
1.2
20
1.5
1.2
20
1.5
30
0.5
70
0.5
30
2
1.79
LVDS
LVDS
Offset binary
Offset binary
Max
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.30
0.05
AD9277
Unit
mV p-p
V
kΩ
pF
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V
V