LTC2635CUD-LMI12#TRPBF Linear Technology, LTC2635CUD-LMI12#TRPBF Datasheet - Page 21

• Manufacturer Part Number: LTC2635CUD-LMI12#TRPBF
• Description: IC DAC 12BIT I2C QUAD 16-QFN
• Manufacturer: Linear Technology

Specifications of LTC2635CUD-LMI12#TRPBF

• Settling Time: 4.4µs
• Number Of Bits: 12
• Data Interface: I²C
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -

The LTC2635 is a family of quad voltage output DACs in
16-pin QFN and 10-lead MSOP packages. Each DAC can
operate rail-to-rail using an external reference, or with its
full-scale voltage set by an integrated reference. Eighteen
combinations of accuracy (12-, 10-, and 8-bit), power-on
reset value (zero-scale, mid-scale in internal reference
mode, or mid-scale in external reference mode), DAC
power-down output load (high impedance or 200kΩ),
and full-scale voltage (2.5V or 4.096V) are available. The
LTC2635 is controlled using a 2-wire I
Power-On Reset
The LTC2635-HZ/-LZ clear the output to zero-scale when
power is first applied, making system initialization con-
sistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2635
contains circuitry to reduce the power-on glitch: the
analog output typically rises less than 5mV above zero-
scale during power on. In general, the glitch amplitude
decreases as the power supply ramp time is increased.
See “Power-On Reset Glitch” in the Typical Performance
Characteristics section.
The LTC2635-HMI/-LMI/-LMX provide an alternative
reset, setting the output to mid-scale when power is first
applied. The LTC2635-LMI and LTC2635-HMI power
up in internal reference mode, with the output set to a
mid-scale voltage of 1.25V and 2.048V, respectively. The
LTC2635-LMX power-up in external reference mode, with
the output set to mid-scale of the external reference. The
LTC2635-LMO powers up in internal reference mode with
all the DAC channels placed in the high-impedance state
(powered-down). Input and DAC registers are set to the
mid-scale code, and only the internal reference is powered
up, causing supply current to be typically 100µA upon
power up. Default reference mode selection is described
in the Reference Modes section.
Power Supply Sequencing
The voltage at REF (Pin 10 – QFN, Pin 7 – MSOP) must
be kept within the range –0.3V ≤ V
Absolute Maximum Ratings). Particular care should be
operation
REF
2
≤ V
C interface.
CC
+ 0.3V (see
taken to observe these limits during power supply turn-
on and turn-off sequences, when the voltage at V
transition.
Transfer Function
The digital-to-analog transfer function is
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and V
LMI/-LMX/-LMO/-LZ) or 4.096V (LTC2635-HMI/-HZ) when
in Internal Reference mode, and the voltage at REF when
in External Reference mode.
I
The LTC2635 communicates with a host using the stan-
dard 2-wire I
1 and 2) show the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The value of
these pull-up resistors is dependent on the power supply
and can be obtained from the I
bus operating in the fast mode, an active pull-up will be
necessary if the bus capacitance is greater than 200pF.
The LTC2635 is a receive-only (slave) device. The master
can write to the LTC2635. The LTC2635 will not acknowl-
edge (NAK) a read request from the master.
START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I
2
C Serial Interface
V
OUT(IDEAL)
2
C device.
2
C interface. The timing diagrams (Figures
=



2
k
N

 V

(
REF
– V
2
REF
C specifications. For an I
REFLO
is either 2.5V (LTC2635-
)
+ V
LTC2635
REFLO

CC
is in
2635fb
2
C