MT47H128M16RT-25E IT:C Micron Technology Inc, MT47H128M16RT-25E IT:C Datasheet - Page 116
MT47H128M16RT-25E IT:C
Manufacturer Part Number
MT47H128M16RT-25E IT:C
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H128M16RT-25E_ITC.pdf
(134 pages)
Specifications of MT47H128M16RT-25E IT:C
Lead Free Status / Rohs Status
Compliant
- Current page: 116 of 134
- Download datasheet (10Mb)
SELF REFRESH
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet
refresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet
prior to CKE going back to HIGH. Once CKE is HIGH (
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for
ments is used to apply NOP or DESELECT commands for 200 clock cycles before
applying any other command.
t
XSNR. A simple algorithm for meeting both refresh and DLL require-
116
t
CKE specifications at least 1 ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x4, x8, x16 DDR2 SDRAM
t
CK specifications at least 1 ×
t
CKE [MIN] has been satisfied
© 2006 Micron Technology, Inc. All rights reserved.
t
CK after entering self
SELF REFRESH
t
CK
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