SDED7-002G-NTY SanDisk, SDED7-002G-NTY Datasheet
SDED7-002G-NTY
Specifications of SDED7-002G-NTY
Related parts for SDED7-002G-NTY
SDED7-002G-NTY Summary of contents
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... IGHLIGHTS mDOC Embedded Flash Drive (EFD) designed for mobile handsets and consumer electronics devices. mDOC H3 is the new generation of SanDisk’s successful mDOC product family, enabling tens of millions of handsets and other mobile devices since the year 2000. mDOC hybrid device combining an embedded thin flash controller and standard flash memory ...
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Rev. 1.2 enabling read/write operations that are identical to a standard, sector-based hard drive. In addition, Embedded TrueFFS employs patented methods, such as virtual mapping, dynamic and static wear-leveling, and automatic block management to ensure high data reliability and maximize ...
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Rev. 1.2 mDOC H3 8Gb/16Gb/32Gb/64Gb - 115-ball Fine-Pitch Ball Grid Array (FBGA) 12x18mm Ball to ball compatible with mDOC G3/G4/H1 families. Enhanced performance by implementation of: Multi-plane operations DMA support Burst operation Dual Data RAM buffering Read/Write Cache Fast partition ...
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... T FFS S MBEDDED RUE TrueFFS (True Flash File System) is SanDisk’s field proven patented flash management software. TrueFFS is embedded within the mDOC H3 device, providing full Block Device functionality to the Operating System (OS) file system via either TrueFFS 7.1 (for supporting both earlier mDOC products and mDOC H3) or the DOC Driver ...
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Rev. 1 EVISION ISTORY Doc. No Revision 92-DS-1205-10 0.1 January 2006 0.2 June 2006 5 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet Date Description Preliminary version RSRVD balls left floating changed from a recommendation to a requirement ...
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Rev. 1.2 Doc. No Revision 1.0 February 2007 6 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet Date Description Ordering information modified Refer to Standard Interface as Demux Current/Power consumption numbers modified Number of partitions available changed from 10 to ...
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... Updated parameter Tcesu Add 10x14 package mechanical description Added note on ball size change of new products Ordering info section updated Added new SanDisk top marking 128KB window updated Updated DMA transfer timing diagram Remove internal pull up of #AVD signal Updated Icc max values for new ...
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Rev. 1 ABLE OF ONTENTS 1. Introduction..............................................................................................................................12 2. Product Overview ....................................................................................................................13 2.1 Product Description ..........................................................................................................13 2.2 Demux (Standard) Interface .............................................................................................14 2.2.1 9x12/10x14/12x18 FBGA Ball Diagrams ............................................................................14 2.2.2 9x12/10x14/12x18 FBGA Signal Description......................................................................16 2.2.3 System Interface .................................................................................................................19 ...
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Rev. 1.2 6. Embedded TrueFFS Technology............................................................................................34 6.1 General Description ..........................................................................................................34 6.2 Operating System Support ...............................................................................................34 6.3 DOC Driver Software Development Kit (SDK)..................................................................35 6.3.1 File Management ................................................................................................................35 6.3.2 Bad-Block Management......................................................................................................35 6.3.3 Wear-Leveling .....................................................................................................................35 6.3.4 Power Failure Management ................................................................................................36 ...
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Rev. 1.2 9.5 mDOC H3 Power Supply Connectivity .............................................................................51 9.6 Connecting Control Signals ..............................................................................................55 9.6.1 Demux Interface..................................................................................................................55 9.6.2 Multiplexed Interface ...........................................................................................................55 9.7 Implementing the Interrupt Mechanism ............................................................................56 9.7.1 Hardware Configuration ......................................................................................................56 9.7.2 Software Configuration........................................................................................................56 9.8 DMA ...
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Rev. 1.2 10.4 Mechanical Dimensions....................................................................................................79 10.4.1 mDOC H3 1Gb (128MB)/2Gb (256MB) ..............................................................................79 10.4.2 mDOC H3 4Gb (512MB)/8Gb (1GB) ..................................................................................80 10.4.3 mDOC H3 8Gb (1GB)/ 16Gb (2GB)/ 32Gb (4GB) / 64Gb (8GB)........................................81 11. Ordering Information...............................................................................................................82 12. Markings...................................................................................................................................83 12.1 mDOC H3 ...
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... Environmental, electrical, timing and product specifications Section 10: Information on ordering mDOC H3 Section 11: Marking information Section 12: For additional information on SanDisk’s flash disk products, please contact one of the offices listed on the back page. © 2007 SanDisk® Corporation mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 12 Introduction ...
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... VERVIEW 2.1 Product Description mDOC H3 is the latest addition to SanDisk’s mDOC product family. mDOC H3, packaged in a small FBGA package and offering densities ranging from 1Gb (128MB) to 16Gb (2GB hybrid device with an embedded flash controller and high capacity flash memory. It uses advanced Flash technologies, enhanced by SanDisk’ ...
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Rev. 1.2 of these features enables mDOC H3 to implement better security schemes to protect the code and data it stores. mDOC H3 can be configured to work with either demux (standard) interface or multiplexed (MUX) interface. Using a multiplexed ...
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Rev. 1.2 9x12/10x14/12x18 FBGA Package RSRVD RSRVD D RSRVD RSRVD E A3 GPIO _ TIMER F RSRVD A 2 RSRVD RSRVD H RSRVD RSRVD ...
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Rev. 1.2 2.2.2 9x12/10x14/12x18 FBGA Signal Description mDOC H3 (115 ball) package ball designations are listed in the signal descriptions, presented in logic groups, in Table 1. Table 1: Demux Interface Signal Description Signal Ball No. Signal Type F10, E10 ...
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Rev. 1.2 Signal Ball No. Signal Type CLK L6 DMARQ# H8 CMOS output IRQ# G9 CMOS output ST/PU/CMOS 3- SCS# G10 ST/PU/CMOS 3- SO H10 ST/PU/CMOS 3- SI J10 ST/PU/CMOS 3- SCLK K10 VCC2 D5 VCC1 E7 VCCQ K6, G4 ...
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Rev. 1.2 Signal Ball No. Signal Type C2, C3, C4, C5, C6, C7, C8, C9, C10, D1, D2, D9, D10, E9, F1, F9, G1, H1, J1, K1, K2, L2, L9, L10, M2, M3, M4, RSRVD M5, M6,M7, M8, M9, M10 ...
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Rev. 1.2 2.2.3 System Interface See Figure 3 for a simplified I/O diagram of a Demux interface to mDOC H3. The power connections and capacitors in this diagram are for illustration only. For detailed recommendations regarding power connections and required ...
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Rev. 1.2 9x12/10x14/12x18 FBGA Package RSRVD D RSRVD RSRVD E VSS GPIO _ TIMER F RSRVD VSS G RSRVD VSS RSRVD VSS H RSRVD RSRVD RSRVD K RSRVD ...
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Rev. 1.2 2.3.2 9x12/10x14/12x18 FBGA Signal Description mDOC H3 FBGA related ball designations are listed in the signal descriptions, presented in logic groups, in Table 2. Table 2: Signal Descriptions for Multiplexed Interface Signal Ball No. Signal Type J8, L8, ...
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Rev. 1.2 Signal Ball No. Signal Type ST/PU/CMOS SCS# G10 ST/PU/CMOS SO H10 ST/PU/CMOS SI J10 ST/PU/CMOS SCLK K10 VCC2 D5 VCC1 E7 VCCQ K6, G4 VCC K5 VSS D3, D4, D7, D8, E2, E3, E4 E8, E10, F2, F3, ...
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Rev. 1.2 Signal Ball No. Signal Type C2, C3, C4, C5, C6, C7, C8, C9, C10, D1, D2, D9, D10, E9, F1, F9, G1, H1, J1, K1, K2, L2, L9, L10, M2, M3, M4, M5, M6,M7, RSRVD M8, M9, M10 ...
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Rev. 1.2 For power connectivity please refer to mDOC H3 power supply connectivity in section 9.5. Figure 5: Multiplexed Interface Simplified I/O Diagram 24 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet Product Overview 92-DS-1205-10 ...
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Rev. 1 HEORY OF PERATION 3.1 Overview mDOC H3 consists of the following major functional blocks, as shown in Figure 6. These components are described briefly below and in more detail in the following sections. • Host ...
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Rev. 1.2 • Flash IF – Physical interface to the Flash Media. • Power and Timing – Analog and clock circuits to provide power and timing for the H3 controller and flash. • Embedded CPU – Runs Embedded TrueFFS SW ...
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Rev. 1.2 3.2.3 Serial Interface The Serial interface (SPI) provides mDOC H3 a secondary interface with debug and programming capabilities. mDOC H3 SPI Interface is configured as Slave. All four combinations of clock phase (CPHA) and clock polarity (CPOL) which ...
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... Error Detection Code/Error Correction Code (EDC/ECC) Since NAND-based flash is prone to errors, it requires unique error-handling capabilities to ensure required reliability. SanDisk’s TrueFFS technology, embedded within mDOC H3, includes a powerful Error Detection Code / Error Correction Code (EDC/ECC), based on the Bose, Chaudhuri and Hocquenghem (BCH) algorithm. Both EDC and ECC are implemented in hardware to optimize performance ...
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Rev. 1 ATA ROTECTION AND 4.1.1 Read/Write-Protected partitions Data and code protection is implemented on a per-partition basis. The user can configure each partition as read protected, write protected, or read and write protected. A protected partition ...
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Rev. 1.2 4.1.4 Unique Identification (UID) Number Each mDOC H3 is assigned a 16-byte UID number. Burned onto the flash during production, the UID cannot be altered and is worldwide unique. The UID is essential for security-related applications, and can ...
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Rev. 1.2 5. DOC ODES OF Figure 7 shows the different modes of mDOC H3 device operation and the interchange between optional modes. mDOC H3 can operate in any one of five basic power modes/states: • Reset ...
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Rev. 1.2 The above power modes are separated into two main groups: • Work mode group – in which the device is active and performs various transactions. • Idle mode group – in which the device is not active. The ...
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Rev. 1.2 5.5 Deep Power-Down Mode While in Deep Power-Down (DPD) mode, the quiescent power dissipation of the mDOC H3 device is further reduced by disabling internal high current consumers (e.g. voltage regulators, input buffers, oscillator etc.) Entering Deep Power-Down ...
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... RUE 6.1 General Description SanDisk’s patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS emulates a hard disk making flash transactions completely transparent to the OS. In addition, since DOC Driver operates under the OS file system layer, and exports standard Block Device API completely transparent to the application ...
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... FAT, registry, etc.). Without any special handling, these pages would wear out more rapidly than other pages, reducing the lifetime of the entire flash. To overcome this inherent deficiency, Embedded TrueFFS uses SanDisk’s patented wear- leveling algorithm. This wear-leveling algorithm ensures that consecutive writes of a specific sector are not written physically to the same page in the flash ...
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Rev. 1.2 Static Wear-Leveling Areas on the flash media may contain static files, characterized by blocks of data that remain unchanged for very long periods of time, or even for the whole device lifetime. If wear-leveling were only applied on ...
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Rev. 1.2 6.3.7 Compatibility Migrating from mDOC G3/G4/H1 and mDOC G3/G4 -based MCP to mDOC H3 and mDOC H3 -based MCP can be done by TrueFFS 7.1. TrueFFS 7.1 supports all mDOC product line including mDOC G3/G4/H1 and mDOC H3. ...
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Rev. 1.2 Note: In future mDOC H3, IPL RAM size is 8KB. For backward compatibility with the memory map, each 32K window is composed of 8K IPL and 3 additional aliases. 38 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet ...
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Rev. 1.2 6.5 8KB Memory Window For the purposes of backward compatibility, mDOC H3 can present an 8KB memory window in the CPU address space, depicted in Figure 9. The addresses described here are relative to the absolute starting address ...
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Rev. 1.2 7. DOC EGISTERS This section describes various mDOC H3 registers and their functions. Address (Hex) Address (Hex) 128KB Window 8KB Window 0030 0070 0080 9400/9422 9402/9424 9404 940C 9416 940E 9418 9410 9412 7.1 Definition ...
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Rev. 1.2 7.3 Registers Description This section describes various mDOC H3 registers and their functions. 7.3.1 Paged RAM Command Register Description: This 8-bit register is used to enable Write to other Paged RAM registers. Address (hex): 0030 (both 8KB window ...
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Rev. 1.2 7.3.3 Paged RAM Unique ID Download Register Description: Writing to this 8 bit register initiates a download of the 16-byte Unique Identification (UID) number to offset 0 of the downloadable section of the IPL RAM. After polling for ...
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Rev. 1.2 D15-D14 D13 Read/Write R R/W Bit name RFU HOLD Reset value 0 0 HOLD See section 9.8.2. LENGTH See section 9.8.2. LATENCY See section 9.8.2. WAIT_STATE See section 9.8.2. BURST_EN Enables burst mode cycles. 0: Burst mode is ...
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Rev. 1.2 WAKE_UP_SEL_BIT Selects the device wake up trigger 0: mDOC H3 CE# is the wakeup trigger. 1: Read access (CE# & OE# assertion) or write access (CE# and WE# assertion) is the wakeup trigger. 7.3.8 DPD Activation Register Description: ...
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Rev. 1.2 1: active low DMA_EN DMA enable bit: 0: DMARQ# is disabled 1: DMARQ# is enabled 7.3.10 DMA Negation Register Description: This 16-bit register controls the negation of DMARQ# signal to the host. Address (hex): 9418 (128KB window) / ...
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Rev. 1.2 7.3.12 Endian Control Register Description: This 16-bit register is used to control the swapping of the low and high data bytes when reading or writing with a 16-bit host. This provides an Endian- independent method of enabling/disabling the ...
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... OS Boot loader from its dedicated partition. SanDisk’s DOC Driver, SDK and utilities enable the construction of a proper mDOC H3 layout in order to support the boot sequence. For a complete description of these tools, refer to the DOC Driver 1 ...
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... When two mDOC H3 devices are cascaded, Paged RAM downloads occur only on the first mDOC H3 device in the cascaded configuration (device-0). For more information on booting from mDOC H3 in Paged RAM Boot mode, please contact your local SanDisk sales office. 48 Booting from mDOC H3 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet ...
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Rev. 1 ESIGN ONSIDERATIONS 9.1 General Guidelines • A typical RISC processor memory architecture may include the following devices: • mDOC H3: Contains the OS image, applications, registry entries, back-up data, user files and data, etc. It ...
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Rev. 1.2 For power connectivity please refer to mDOC H3 power supply connectivity in section 9.5. Notes: 1. mDOC edge-sensitive device and care should be taken to prevent excessive ringing on the CE#, OE# and WE# signals. ...
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... The values listed are the minimum required values and may be increased. However any major deviations from the values specified above should be verified with SanDisk. 4. The values of capacitors listed as recommended may be modified based upon the specific behavior of the system power supply and board layout. These are bypass capacitors and they are required to minimize ripples on the power supply inputs ...
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Rev. 1.2 7. The series inductance of the capacitors marked as required should be less than 15nH. 8. For this configuration, we recommend that the 0.1uF capacitor will be located close to the VCC ball and the 10nF capacitor will ...
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Rev. 1.2 Figure 13: mDOC H3 power connection for 3.3v core/3.3v I/O Figure 14: mDOC H3 power connection for 3.3v core/1.8v I/O 53 Design Considerations mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 92-DS-1205-10 ...
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Rev. 1.2 Figure 15: mDOC H3 power connection for 1.8v core/1.8v I/O 54 Design Considerations mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 92-DS-1205-10 ...
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Rev. 1.2 9.6 Connecting Control Signals 9.6.1 Demux Interface When using a demux NOR-like interface, connect the control signals as follows: • A[16:0] – Connect these signals to the host address signals (see Section 9.10 for platform-related considerations). The A0 ...
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Rev. 1.2 cycle made to mDOC must observe the multiplexed mode protocol. See Section 10 for more information about the related timing requirements. Please refer to Section 2.3 for ballout and signal descriptions, and to Section 10 for timing specifications ...
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Rev. 1.2 2. Level DMARQ# output is asserted while the data is available for read, or data can be accepted for write. The EDGE bit is set to 0 for this mode. The following steps are required in order to ...
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Rev. 1.2 9.8.2.1 Read Mode The LATENCY field controls the number of clock cycles between mDOC H3 sampling CE# being asserted and when the first word of data is available to be latched by the host. This number of clock ...
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Rev. 1.2 Burst CLK CE OE AVD Data Valid address Notes: 1. Note: AVD must be asserted on the following clock after the assertion of CE collision should be allowed between the AVD and OE signal. 9.8.2.2 Write ...
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Rev. 1.2 9.9 Device Cascading Up to two devices can be cascaded with no external decoding circuitry. Figure 19 illustrates the configuration required to cascade two devices on the host bus (only the relevant cascading signals are included in this ...
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Rev. 1.2 9.10 Platform-Specific Issues This section discusses hardware design issues for major embedded RISC processor families. 9.10.1 Wait State Wait states can be implemented only when mDOC H3 is designed in a bus that supports a Wait state insertion, ...
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Rev. 1.2 16-Bit (Word) Data Access Mode The mDOC bit wide device. All accesses to and from the device are 16 bit wide. mDOC H3 address lines should be connected to system host address lines, as depicted ...
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... TrueFFs 7.1 Software Development Kit (SDK) • XP utilities: o DFormat o DImage o DInfo • Documentation: o Data sheet o Application notes o Technical notes o Articles o White papers Please visit the SanDisk website (www.sandisk.com) for the most updated documentation. 63 Design Considerations mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 92-DS-1205-10 ...
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Rev. 1.2 10 RODUCT PECIFICATIONS 10.1 Environmental Specifications 10.1.1 Operating Temperature Product Ordering Info MD2534-XXX-YY SDE-ZZ-XXXY-BBB 10.1.2 Thermal Characteristics Junction to Case (θ 10.1.3 Humidity 10% to 90% relative, non-condensing. 10.2 Electrical Specifications 10.2.1 Absolute Maximum Ratings Parameter ...
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Rev. 1.2 2. When operating mDOC H3 with separate power supplies for VCCQ/VCC/VCC1/VCC2 recommended to turn the supplies on and off simultaneously. Providing power separately (either at power-on or power-off) can cause excessive power dissipation. Damage to the ...
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Rev. 1.2 10.2.3.2 3.3V Core, 1.8V I/O Symbol Parameter VCCQ I/O power supply VCC2 Internal supply VCC Device supply VCC1 Internal supply Input High-level Voltage VIH Input Low-level Voltage VIL II Input Leakage Current IOZ Tri-State output leakage current Hysteresis ...
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Rev. 1.2 10.2.3.3 3.3V Core, 3.3V I/O Symbol Parameter VCCQ I/O power supply VCC2 Internal supply VCC Device supply VCC1 Internal supply VIH Input High-level Voltage VIL Input Low-level Voltage II Input Leakage Current IOZ Tri-State output leakage current Vhys ...
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Rev. 1.2 10.3 Timing Specifications 10.3.1 Operating Conditions Timing specifications are based on the conditions defined in Table 12. Parameter Ambient temperature (TA) Supply Voltage (VCCQ) Input fall CLK, SCS#, SI, and rise SO, SCLK time (10%- All other inputs ...
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Rev. 1.2 10.3.2 Demux Asynchronous Read Timing Figure 22: Demux Asynchronous Read Timing CE OE Tsua Address Data Figure 23: Demux Read Timing – Asynchronous Boot Mode Table 13: Demux Asynchronous Read Timing Parameters Symbol Tsua Address setup time (Figure ...
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Rev. 1.2 10.3.3 Demux Asynchronous Write Timing Figure 24: Demux Asynchronous Write Timing Table 14: Demux Asynchronous Write Timing Parameters Symbol Tasu Address setup Tah Address hold time Tdsu Data setup Tdh Data hold Tw(ceh) CE# high pulse width Tw(cel) ...
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Rev. 1.2 Table 15: Multiplexed Asynchronous Read Timing Parameters Symbol Tasu Address setup Tah Address hold Taccs Access time Tdh Data hold Tavd AVD# pulse width Tw(oel) OE# low pulse width Tw(oeh) OE# high pulse width Tavdoe AVD rising to ...
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Rev. 1.2 10.3.6 Demux Burst Read Timing Figure 27: Demux Burst Read Timing Diagram Table 17: Demux Burst Read Timing Parameters Symbol Tasu Address setup Tah Address hold Tcesu CE# setup Tacc Access time Tcyc Burst clock cycle time Tdh ...
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Rev. 1.2 10.3.7 Demux Burst Write Timing Burst CLK Tces u CE Tah Tasu Address A0 Tweh Twesu WE Data Figure 28: Demux Burst Write Timing Diagram Table 18: Demux Burst Write Timing Parameters Symbol Tasu Address setup Tah Address ...
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Rev. 1.2 10.3.8 Multiplexed Burst Read Timing Burst CLK Tcesu CE OE Tavdh Tavdsu AVD Tasu Tah Data Valid address Figure 29: Multiplexed Burst Read Timing Diagram Table 19: Multiplexed Burst Read Timing Parameters Symbol Tasu Address setup Tah Address ...
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Rev. 1.2 10.3.9 DMA Request Timing Diagram 10.3.9.1 Asynchronous Data Transfer Table 20 lists DMA request timing parameters and Figure 30 shows the DMA request timing diagram in Asynchronous data transfer. CE/OE DMARQ# Figure 30: DMA Request Timing Diagram (Asynchronous ...
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Rev. 1.2 10.3.10 SPI Timing Table 22 lists SPI slave timing parameters. Figure 32 and Figure 33 show the SPI slave timing diagram. Symbol Description tw(SCLK1) SCLK high pulse width tw(SCLK0) SCLK low pulse width tcyc(SCLK) SCLK period tsu(SI) SI ...
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Rev. 1.2 10.3.11 Power Supply Sequence When operating mDOC H3 with separate power supplies powering the VCCQ, VCC, VCC1 or VCC2 rails desirable to turn the supplies on and off simultaneously. Providing power to one supply rail and ...
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Rev. 1.2 Symbol T (VCC-RSTIN) VCC/VCCQ stable to RSTIN# REC T (RSTIN) RSTIN# asserted pulse width W T (BUSY0) RSTIN (BUSY1) RSTIN (VCC-BUSY0) VCC/VCCQ stable to BUSY# P Tsu (RSTIN-AVD) RSTIN# Tsu (BUSY-CE) BUSY# Trise (RSTIN) ...
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... FBGA 128MB (1Gb) dimensions: 9.0 ±0 12.0 ±0 1.1 ±0.1 mm Ball pitch: 0.8 mm 9.0 0. INDEX 4X 0.15 Top Symbol Ordering info b MD2534-d2G-X-P b SDED7-256M-N9 Figure 35: Mechanical Dimensions 9x12 FBGA Package 79 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 1.1±0.1 0.26±0.04 b Side Dimensions in mm Min Nom Max 0.41 ...
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Rev. 1.2 10.4.2 mDOC H3 4Gb (512MB)/8Gb (1GB) FBGA dimensions: 10.0 ±0 14.0 ±0 1.1 ±0.1 mm Ball pitch: 0.8 mm 10±0.1 INDEX Top Figure 36: Mechanical Dimensions 10x14 FBGA Package 80 mDOC H3 EFD Featuring ...
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... H3 8Gb (1GB)/ 16Gb (2GB)/ 32Gb (4GB) / 64Gb (8GB) FBGA dimensions: 12.0 ±0 18.0 ±0 1.3 ±0.1 mm Ball pitch: 0.8 mm Symbol Ordering Info h SDED7-001G-NT h SDED7-002G-NT h SDED5-002G-NC h SDED5-004G-NC h SDED5-008G-NC Figure 37: Mechanical Dimensions 12x18 FBGA Package 81 Product Specifications mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet Max Height(mm) 1 ...
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... O I RDERING NFORMATION See Table 24 for mDOC H3 devices available and the associated order information. Ordering Code MD2534-d1G-X-P MD2534-d1G-X-P/Y MD2534-d2G-X-P MD2534-d2G-X-P/Y SDED7-256M-N9T SDED7-256M-N9Y SDED7-512M-NAT SDED7-512M-NAY MD2533-d8G-X-P MD2533-d8G-X-P/Y SDED5-001G-NAT SDED5-001G-NAY MD2533-d16G-X-P MD2533-d16G-X-P/Y SDED5-002G-NCT SDED5-002G-NCY SDED5-004G-NCT SDED5-004G-NCY SDED5-008G-NCT SDED5-008G-NCY Notes: 1. SDE Product Codes: T suffix specifies shipment in Tape & Reel; Y suffix specifies shipment in trays ...
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Rev. 1.2 12. M ARKINGS 12.1 mDOC H3 1Gb (128MB)/2Gb (256MB) Markings for MD2533-d1G XXX and MD2533-d26G XXX products: First row: Logo Second row: Product name Third row: Ordering information Fourth row: Production information: yyww - Year and week xx ...
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Rev. 1.2 12.2 mDOC H3 8Gb (1GB)/16Gb (2GB) Markings for MD2533-d8G XXX and MD2533-d16G XXX products: First row: Product name Second row: Logo Third row: Ordering information Fourth row: Production information: yyww - Year and week xxx - Product status: ...
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... Third row: Ordering information Fourth row: Internal use Fifth row: country of origin i.e ‘TAIWAN’ or ‘CHINA’ ‘ES’ or ‘CS’. There will marking for products in mass production. Figure 40: Example of SDED7-512M-NA Product Marking 85 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet Markings 92-DS-1205-10 ...
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... SanDisk IL shall not be liable for any loss, injury or damage caused by use of the Products in any of the following applications: Special applications such as military related equipment, nuclear reactor control, and aerospace ...
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... Per SanDisk IL’s Terms and Conditions of Sale, the user of SanDisk IL’s products in life support applications assumes all risk of such use and indemnifies SanDisk IL against all damages. See “Disclaimer of Liability". Accordingly, in any use of the Product in life support systems or other applications where failure could cause injury or loss of life, the Product should only be incorporated in systems designed with appropriate and sufficient redundancy or backup features ...