S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 10

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
Transmit Input Pin Description
Parallel Input Data (PINP/N[15:0]) –
External Pin
PINP/N[15:0] is the LVDS parallel data input bus which
is multiplexed 16:1 and transmitted serially at STS-192/
10 GbE/10G FC rates. This data is aligned with the
Parallel Input Clock (PICLKP/N). Bit 15 is the Most
Significant Bit (MSB). This bus is typically connected to
a framer, mapper or digital wrapper (e.g. GANGES, or
RUBICON). These inputs are internally terminated 100
 line-to-line and are either internally biased for AC
coupling or DC level shifted for DC coupling. See
LVDS_INPUT_AC_EN control description.
Parallel Input Clock (PICLKP/N) –
External Pin
PICLKP/N is the LVDS 622.08 MHz (or equivalent
FEC/10 GbE/10G FC Rate) input clock to which the
Parallel Input Data (PINP/N[15:0]) is aligned. PICLKP/
N is a delayed version of the PCLK. This clock is used
to clock the data into the S19252 FIFO. These inputs
are internally terminated 100  line-to-line and are
either internally biased for AC coupling or DC level
shifted for DC coupling. See LVDS_INPUT_AC_EN
control description.
LVDS Input AC Enable
(LVDS_INPUT_AC_EN) – Register
The
which selects between AC or DC coupling for the PINP/
N[15:0] and PICLKP/N (LVDS) inputs. When active
(default), the LVDS inputs will provide bias for AC
coupled inputs. When disabled the LVDS inputs will
provide DC level shifting for DC coupled inputs.
TX Ref. Select (TXREFA_NOTB) –
Register
The TXREFA_NOTB is the active high input which
selects
reference clock input. When the TXREFA_NOTB is
active (default), the REFCLKAP/N is selected to be the
input for the TX Reference Frequency for the Clock
Synthesis Unit (CSU). If the TXREFA_NOTB is inactive,
the REFCLKBP/N is used as the reference clock source
for the CSU. See Table 1. This input is only accessible
through the serial bus registers.
10
LVDS_INPUT_AC_EN is an active high input
between
REFCLKAP/N
AppliedMicro - Confidential and Proprietary
or
REFCLKBP/N
Table 1:
SONET Rate Select (SONET_RATESEL)
– Register
SONET Rate Select. When active, the device is
operating at SONET rate. When inactive, it is operating
at either 10 G FC or GbE rate.
GbE Rate Select (GBE_RATESEL) –
Register
GbE Rate Select. When active, the device is operating
at 10 GbE or FC rate. The signal is only functional
when SONET_RATESEL is inactive.
TX Ref. Rate Select (TXREFSEL) –
Register
The TX Reference Rate Select (TXREFSEL) input
selects between a 155.52 MHz or 622.08 MHz (or
equivalent FEC/10 GbE/10G FC rate) reference clock.
When
GBE_RATESEL is active, 10 GE reference (156.25
MHz) or FC reference (159.375 MHz) is used. When
the SONET_RATESEL is active, and TXREFSEL is
inactive, the common reference 155 MHz clock is
used; if TXREFSEL is set active, then 622 MHz is
used. See Table 2, Transmit Reference Rate Select for
the CSU. These inputs are only accessible through the
serial bus registers.
Table 2:
TXREFA_N
Note that the source of TXREFCLK is either REFCLKA or REFCLKB. The
default is REFCLKAP/N.
REF
SEL
TX
X
0
1
OTB
1
0
SONET_
SONET_RATESEL
RATE
Transmit Reference Source Select
Transmit Reference Rate Select
SEL
0
1
1
GBE_
RATE
SEL
Reference Clock Source
1
X
X
REFCLKAP/N
REFCLKBP/N
(10GE) 156.25 or (FC) 159.375 (or
155 (or equiv. FEC rate) x64
622 (or equiv. FEC rate) x16
and Rate Multiplier
is
Reference Clock
equiv. FEC rate) x66
(MHz)
inactive,
Revision 5.03
and