S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 14

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
Automatic FIFO Initialization
(AUTO_FIFO_INIT) – Register
This active high control input internally connects the
transmit FIFO signals (PHERR output and PHINIT
input) and automatically initializes the FIFO in case of a
PCLK/PICLK set-up or hold time violation. This input is
only accessible through the serial bus register.
Transmit Built-In Self Test Enable
(TX_BIST_EN) – Register
This active high input enables the transmit built-in self
test mode. For normal system operation, TX_BIST_EN
should be programmed to logic low. The S19252 goes
in the BIST mode when TX_BIST_EN is programmed
to logic high. Once the TX_BIST_EN is programmed to
logic high, the PRBS generator will start sending the
PRBS/user defined pattern (see Table 13 for details).
The checker will be activated but will not start checking
for the valid data pattern until RX_LOCKDET is active.
This function is accessible through the serial bus regis-
ter. Note - While TX BIST is enabled the parallel input
bus will not provide a TX_DATA_SWAP even if
TX_DATA_SWAP is enabled.
Transmit Built-In Self Test Clear
(TX_BIST_CLR) – Register
This active high level sensitive input clears the transmit
built-in self test error (TX_BIST_ERR). For normal sys-
tem operation, TX_BIST_CLR should be programmed
to logic low. The TX_BIST_ERR flag can be cleared by
asserting the TX_BIST_CLR in the BIST mode or by
resetting (RSTB) the S19252. TX_BIST_CLR is an
active high level sensitive input. In order for the trans-
m i t c h e c k e r t o c l e a r t h e T X _ B I S T _ E R R f l a g ,
TX_BIST_CLR must be asserted high. This input is
only accessible through the serial bus register.
Parallel Input Data Bus Swap
(TX_DATA_SWAP) – Register
This input reverses the order of the parallel input data
bus (PINP/N[15:0]). This makes routing easier with
configurations requiring Data Bus bit order reversal.
AppliedMicro recommends that DATA_SWAP input be
programmed to logic low (Default) when S19252 is
used with the 300-pin MSA connector. The S19252
should be placed on the top side of the module when
used with the 300-pin MSA connector. See Table 22 for
details. This input is only accessible through the serial
14
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bus register. TX BIST results are invalid while
TX_DATA_SWAP is enabled.
Transmit Output Pin Description
Transmit Serial Data (TSDP/N) –
External Pin
The differential High Speed CML Transmit Serial Data
(TSDP/N) output is the serialized version of the
incoming parallel data stream. This output is typically
used to drive the laser driver.
Parallel Clock (PCLKP/N) – External Pin
The LVDS Parallel Clock (PCLKP/N) output is a
622.08 MHz (or equivalent FEC/10 GbE/10 GFC rates)
internally generated clock output used to coordinate
parallel data transfers with upstream logic. The
PCLKP/N is directly derived from the CSU REFCLKP/N
in the normal operating mode. PCLK is the divided-
down version of the internal TXCLK. PCLK is used to
clock data out of the upstream devices (framer/
mapper). PCLK is also used internally to clock data
from the FIFO into the parallel-to-serial shift register.
See Table 35 for LVDS termination.
155.52 MHz Clock Output
(TX_155MCKP/N) – External Pin
The LVDS 155.52 MHz Clock Output (or equivalent
FEC/10 Gigabit Ethernet rate) TX_155MCKP/N pin is
an internally generated clock output used to drive the
reference clock input of the receive section of the
S19252 in the normal mode of operation. The
TX_155MCKP/N cannot be used as the reference
clock for the receive section of the S19252 in the
RLPTIME. See Table 35 for LVDS termination.
Transmit Lock Detect (TX_LOCKDET) –
Register and External Pin
The active high transmit Lock Detect is an LVCMOS
output. This asynchronous output will be active high
once the internal PLL has locked to the clock provided
on the CSU REFCLK input. The TX_LOCKDET output
goes active (high) when the PCLK is within 500 ppm
from the CSU REFCLK. This output can be accessed
through the serial bus register and through an external
LVCMOS pin.
Revision 5.03