S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 21

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Common Input Pin Description
Reset (RSTB) – External Pin
This active low LVCMOS Reset (RSTB) input
asynchronously resets the device. All clocks, including
PCLK, are disabled during reset. For normal system
operation, V
This input should be active for 100 ns to accurately
reset the device. This input can be accessed through
the external LVCMOS input pin.
Diagnostic Loopback Enable (DLEB) –
Register
The DLEB is an active low input that selects the
diagnostic
Transmitter Data (TSD) is routed internally from the
transmitter to the receiver. When DLEB mode is
enabled, the received parallel data from the framer/
mapper transmit path is routed back to the receive
parallel data path of the framer/mapper. This mode
allows the digital side of the node to be isolated from
the rest of the network. The received serial data,
SERDATIP/N, will not be passed on to the framer/
mapper. The network, however, will receive the aligned
high-speed data TSD, when DLEB mode is active. This
input is accessible through the serial bus register.
Line Loopback Enable (LLEB) –
Register
This active low input selects line loopback mode. In this
mode, the internal receiver data (RSD[15:0]) is routed
internally from the receiver to the transmitter. When the
LLEB is enabled, the parallel output data RSD[15:0]
(internal signal) is routed to the parallel input data path
PIN[15:0]. The parallel data outputs POUT[15:0] and
parallel output clock POCLK are accessible in the
LLEB mode.
Case 1. XVCO select input is active. When LLEB and
XVCO inputs are active, the internal POCLK acts as
the timing source for the CSU block. In this case, the
recovered POCLK is fed into the phase detector block.
The output of the phase detector block is fed into the
external loop filter and VCO. The output of the external
VCO is fed into the CSU_IN input, which would be
selected as the reference clock for the CSU block. The
jitter transfer specification, as defined in GR-253-
CORE, is met in this mode.
Revision 5.03
DD_3.3V
loopback
should be connected to RSTB input.
mode.
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In
this
mode,
the
Case 2. XVCO select input is inactive. When LLEB
input is active and XVCO input is inactive, the internal
recovered serial clock (RSCLK) acts as the timing
source for the CSU block. In this case, the output of the
phase detector block is not used. The jitter transfer
specification, as defined in GR-253-CORE, is not met
in this mode.
This mode allows the network to be isolated from the
digital side of the node (framer/mapper gets bypassed).
See Table 11, Line Loopback Enable Mode. This input
is only accessible through the serial bus register.
Table 11: Line Loopback Enable Mode
The BOLD CELLS denote the default state
Reference Loop Timing (RLPTIME) –
Register
This active high input selects the reference loop timing
mode. In this mode, the transmitter CSU utilizes the
receiver POCLK instead of the transmitter external
reference clock (CSU_REFCLK). High-speed data
flows into the receiver section of the transceiver and is
deserialized and aligned before being transmitted to
the framer/mapper. The transmitted POCLK provides
the timing for the receive section of the framer/mapper.
Since some framer/mappers operate with a fixed-size
internal FIFO, the framer/mapper transmit section will
have to be synchronized with its receive section to
avoid over/under flowing of the internal FIFO. In
RLPTIME mode, the transmit clock, or PCLK, is
generated from the outbound POCLK with the use of
the transceiver’s internal clock synthesizer unit.
XVCO select input should be programmed to logic high
in the RLPTIME mode. The external VCO should be
used in the RLPTIME mode.
LLEB
0
0
1
XVCO
X
0
1
Line Loopback Active. Internal
RSCLK will be the timing source for
the transmitter while XVCO input is
inactive.
Line Loopback Active. POCLK (Out-
put of the external XVCO that is fed
into the CSU_IN input) will be the tim-
ing source for the transmitter while
XVCO input is active.
Line Loopback inactive.
Mode of Operation/ Clock Source
S19252 Data Sheet
21