21143TD Intel, 21143TD Datasheet
21143TD
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21143TD Summary of contents
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... Provides glueless 32-bit PCI bus master interface. Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Preliminary Datasheet Contains large independent receive and transmit FIFOs ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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OVERVIEW .......................................................................................................................... 1 1.1 General Description ............................................................................................................ 2 1.2 Microarchitecture ................................................................................................................ 3 2.0 PINOUT ........................................................................................................................................... 5 2.1 Signal Reference Tables .................................................................................................... 7 2.2 Signal Reference Tables .................................................................................................... 9 2.3 Pin Tables.........................................................................................................................15 2.4 Signal Grouping by Function ............................................................................................17 3.0 ...
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... Overview The Intel 21143 PCI/CardBus* 10/100-Mb/s Ethernet LAN Controller (21143) supports the peripheral component interconnect (PCI) bus or CardBus. It provides a direct interface connection to the PCI bus and adapts easily to the CardBus and most other standard buses. The 21143 software interface and data structures are optimized to minimize the host CPU load and to allow for maximum flexibility in the buffer descriptor management ...
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Supports full-duplex operation on both MII/SYM and 10BASE-T ports. • Provides internal and external loopback capability on all network ports. • Supports IEEE 802.3 and ANSI 8802-3 Ethernet standards. Other Features: • Provides MicroWire* interface for serial ROM ...
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Microarchitecture The following list describes the 21143 hardware components, and of the 21143: • PCI/CardBus interface—Includes all interface functions to the PCI and CardBus bus; handles all interconnect control signals; and executes DMA and I/O transactions • Boot ROM ...
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DMA Interface 4 Board Control PCI/CardBus and LEDs General- PCI/CardBus Purpose Interface Register FIFO 16 Wake-Up RxM Controller SIA Interface NWAY AUI 10BASE-T Interface 10 Mb/s 10 Mb/s Figure 1. 21143 Block ...
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Pinout The 21143 is offered in two package styles: a 144-pin low-profile quad flat pack (LQFP) and a 144-pin metric quad flat pack (MQFP). The tables in this section provide a description of the pins and their respective signal ...
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21143 vdd 1 vdd 2 vss 3 tp_td-- 4 tp_td- 5 tp_td+ 6 tp_td++ 7 vdd 8 tp_rd+ 9 ...
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Signal Reference Tables Table 2 provides an alphabetical list of the 21143 logic names and their pin numbers. provides a list of the 21143 power pin numbers. Preliminary Datasheet 21143 Table 3 7 ...
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Signal ad<0> ad<1> ad<2> ad<3> ad<4> ad<5> ad<6> ad<7> ad<8> ad<9> ad<10> ad<11> ad<12> ad<13> ad<14> ad<15> ad<16> ad<17> ad<18> ad<19> ad<20> ad<21> ad<22> ad<23> ad<24> ad<25> ad<26> ad<27> ad<28> ad<29> ad<30> ad<31> aui_cd– aui_cd+ 8 Table 2. ...
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Signal tp_td+ + xtal1 Signal vdd (3.3 V) vddac (3.3 V) vdd_clamp ( 3.3 V) 2.2 Signal Reference Tables The functional grouping of each pin is listed in The following terms describe the 21143 pinout: • Address phase ...
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Table 4 provides a functional description of each of the 21143 signals. These signals are listed alphabetically. Signal Type ad<31:0> I/O aui_cd– I aui_cd+ I aui_rd– I aui_rd+ I aui_td– O aui_td+ O br_a<0>/ O cb_pads_l br_a<1> O br_ad<7:0> ...
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Signal Type devsel_l I/O frame_l I/O gep<0>/ I/O aui_bnc gep<1>/activ I/O gep<2>/ rcv_match/ I/O wake gep<3>/link I/O Preliminary Datasheet Table 4. Functional Description of 21143 Signals (Sheet Pin Number Device select is asserted by the target of ...
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Signal Type gnt_l I idsel I int_l O/D iref I irdy_l I/O mii_clsn/ I sym_rxd<4> mii_crs/sd I mii_dv I mii_mdc O mii_mdio I/O mii/sym_rclk I mii_rx_err/ I/O sel10_100 12 Table 4. Functional Description of 21143 Signals (Sheet 3 of ...
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Signal Type mii/ I sym_rxd<3:0> mii/sym_tclk I mii/ O sym_txd<3:0> mii_txen/ sym_txd<4> O par I/O pci_clk I perr_l I/O req_l O rst_l I serr_l O/D sr_ck O sr_cs O sr_di O sr_do I Preliminary Datasheet Table 4. Functional Description of ...
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Signal Type stop_l I/O tck I tdi I tdo O tms I tp_rd– I tp_rd+ I tp_td– O tp_td– – O tp_td+ O tp_td trdy_l I/O vcap_h I vdd P vddac P vdd_clamp P vss P xtal1 ...
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Signal Type xtal2 O 2.3 Pin Tables This section contains four types of pin tables: • Table 5 lists the input pins. • Table 6 lists the output pins. • Table 7 lists the input/output pins. • Table 8 lists ...
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Signal ad<31:0> br_a<0>/cb_pads_l br_ad<7:0> clkrun_l c_be_l<3:0> devsel_l frame_l gep<0>/aui_bnc gep<1>/activ a. The active level is controlled by bit MiscHwOptions<1> (PME_STSCHG) in the serial ROM. Signal int_l 16 Table 7. Input/Output Pins Active Level Signal — gep<2>/rcv_match/wake High for br_a<0>, ...
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Signal Grouping by Function Table 9 lists the signals according to their interface function. . Interface PCI/CardBus MII/SYM network port Test access port Serial ROM port Boot ROM port Power General-purpose port and LEDs Preliminary Datasheet Table 9. Signal ...
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Interface Network connection 18 Table 9. Signal Functions (Sheet Function Analog phase-locked loop logic iref, vcap_h AUI collision data aui_cd–, aui_cd+ aui_rd–, aui_rd+, aui_td–, AUI transmit and receive data aui_td+ Crystal oscillator xtal1, xtal2 Twisted-pair transmit ...
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Electrical and Environmental Specifications This section contains the electrical and environmental specifications for the 21143. Caution: Stresses greater than the maximum or less than the minimum ratings can cause permanent damage to the 21143. Exposure to the maximum or ...
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Power Specifications The values in Table 12 network data rate of 10/100 Mb/s for MII for legacy power-saving modes. Mode After power-up Normal Snooze Sleep 1. Typical: vdd = 3 Maximum: vdd ...
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PCI and CardBus I/O Voltage Specifications The 21143 meets the I/O voltage specifications listed in . Symbol Parameter V Input high voltage ih V Input low voltage Input leakage current i V Output high voltage oh ...
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System Bus Reset System bus (PCI or CardBus) reset (rst_l asynchronous signal that must be active for at least 10 system bus (PCI or CardBus) clock (pci_clk) cycles. characteristics, and pci_clk rst_l Internal Reset Symbol Parameter ...
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Clock 3.3-V Clock 0.475 * vdd_clamp 0.325 * vdd_clamp Table 17. PCI and CardBus Clock Timing Specifications Symbol Tcycle Cycle time Thigh pci_clk high time Tlow pci_clk low time 1 Tr/Tf pci_clk slew rate 1. Rise and fall times ...
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Other PCI and CardBus Signals Figure 5 shows the timing diagram characteristics for other PCI and CardBus signals and lists their timing specifications. This timing is identical to the timing for the general-purpose register signals. Clk Output Input ...
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AUI and Twisted-Pair DC Specifications Table 19 lists the dc specifications for the AUI and twisted-pair parts of the SIA. . Symbol AUI Pins Transmit differential output V od voltage (aui_td±) Transmit differential output idle 1 V odi voltage ...
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Serial Interface Attachment Specifications This section describes the dc specifications and timing limits of the SIA unit. 3.6.1 Serial Clock Timing Figure 6 shows the serial clock (TTL or CMOS) timing characteristics, and clock timing specifications. Symbol 1 ...
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Internal SIA Mode AUI Timing—Transmit Figure 7 shows the internal SIA transmit timing characteristics for the AUI, and internal SIA transmit timing limits for the AUI. xtal1 aui_td+ aui_td- Table 21. Internal SIA Mode AUI Timing Specifications—Transmit Symbol aui_td+, ...
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Internal SIA Mode AUI Timing—Receive Figure 8 shows the internal SIA receive timing characteristics for the AUI, and internal SIA receive timing limits for the AUI. Tudo 3.6.4 Internal SIA Mode AUI Timing—Collision Figure 9 shows the internal ...
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Internal SIA Mode 10BASE-T Interface Timing—Transmit Figure 10 shows the internal SIA transmit timing characteristics for the 10BASE-T interface, and Table 23 lists the internal SIA transmit limits. xtal1 tp_td+ Tpdc tp_td-- tp_td- tp_td++ Figure 10. Internal SIA Mode ...
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Internal SIA Mode 10BASE-T Interface Timing—Receive Figure 11 shows the internal SIA receive timing characteristics for the 10BASE-T interface, and Table 24 lists the internal SIA receive limits for the 10BASE-T interface. Tsn tp_rd+/- Tsf Figure 11. Internal ...
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Internal SIA Mode 10BASE-T Interface Timing—Idle Link Pulse Figure 12 shows the internal SIA idle link pulse timing characteristics for the 10BASE-T interface, and Table 25 lists the internal SIA idle link pulse limits for the 10BASE-T interface. tp_td+ ...
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MII Interface Specifications Table 26 lists the specifications for the MII interface. Symbol Definition V Output high voltage oh V Output low voltage ol V Input high voltage ih V Input low voltage il I Input current in ...
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Symbol 1 Tcc mii/sym_tclk cycle Tch mii/sym_tclk high time Tcl mii/sym_tclk low time 3 Tcr mii/sym_tclk rise time 3 Tcf mii/sym_tclk fall time mii_tclk rise to mii_txen valid time or 4 Trv mii/sym_tclk rise to mii/sym_txd valid ...
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MII/SYM 10/100-Mb/s Timing—Receive Figure 14 shows the MII/SYM port receive timing characteristics, and port receive timing limits. mii/sym_rclk mii/sym_rxd<3:0> mii_dv Symbol 1 Tcc mii/sym_rclk cycle time Tc mii/sym_rclk high time Tcl mii/sym_rclk low time 3 Tcr mii/sym_rclk rise ...
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SYM 10/100-Mb/s Timing—Signal Detect Figure 15 shows the SYM port signal detect timing characteristics, and signal detect timing limits. sym_rclk sd Symbol Definition sd setup (both rise and fall transactions Tts sym_rclk fall time sd hold (both ...
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MII 10/100-Mb/s Timing—Carrier Sense and Collision Figure 17 shows the MII port carrier sense and collision timing characteristics, and the MII port carrier sense and collision timing limits. Table 31. MII Port Timing Limits—Carrier Sense and Collision Symbol ...
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Boot ROM Port Timing This section describes the boot ROM port timing. 3.10.1 Boot ROM Read Timing Figure 18 shows the boot ROM read timing characteristics, and timing limits. br_ad<7:0> br_a<1> br_a<0> br_ce_l Symbol Tavav Read cycle time Tavqv ...
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Boot ROM Write Timing Figure 19 shows the boot ROM write timing characteristics, and timing limits. br_ad<7:0> br_a<1> br_a<0> br_ce_l 1 Symbol Tavav Write cycle time Teleh br_ce_l pulse width Taveh Address setup to br_ce_l going high Tdveh ...
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Serial ROM Port Timing Figure 20 shows the serial ROM port timing, and identical to the timing for the MII management signals (mii_mdio and mii_mdc). Symbol 1 Tsr 1 Tsf 1. Parameter design guarantee. 3.12 External Register Timing Figure ...
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Symbol Parameter Teleh br_ce_l pulse width Read Timing Tpd br_ce_l low to br_ad<7:0> valid high 1 Tehqz br_ce_l high to br_ad<7:0> high impedance Write Timing Ts Data setup time prior to br_ce_l Th Data hold after br_ce_l high 1. ...
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Joint Test Action Group—Test Access Port This section provides the joint test action group (JTAG) test access port specifications. 3.13.1 JTAG DC Specifications Table 37 lists the dc specifications for the JTAG pins . Symbol V Output high voltage ...
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JTAG Boundary-Scan Timing Figure 23 shows the JTAG boundary-scan timing, and relationships. tck tms tdi tdo Symbol Tms_s Tms_h Tdi_s Tdi_h Tdo_d 1 Tck_r 1 Tck_f Tck_cycle 1. Parameter design guarantee. 42 Table 38 Tck_cycle Tck_f Tms_s Tms_h ...
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Mechanical Specifications The 21143 is contained in either a 144-pin LQFP package type or a 144-pin MQFP package type. Figure 24 shows the mechanical layout of the LQFP, and dimensions in millimeters. Figure 25 shows the mechanical layout of ...
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A2 Detail "A" Pin 1 144-Pin LQFP See Detail "A" ddd (LL Figure 24. 144-Pin LQFP Package ...
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Symbol ccc ddd The value for this measurement is for reference only 2. ANSI Y14.5M–1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2, defines Basic Dimension ...
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Pin 1 144-Pin MQFP (A) A2 Detail "A" See Detail "A" ddd Note: All dimensions are in millimeters. ...
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Symbol ccc ddd The value for this measurement is for reference only. 2. ANSI Y14.5M–1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2, defines Basic Dimension ...
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... Intel World Wide Web Internet site: http://www.intel.com Copies of documents that have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-332-2717 or by visiting Intel’s website for developers at: http://developer.intel.com You can also contact the Intel Massachusetts Information Line or the Intel Massachusetts Customer Technology Center ...