PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 143
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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SC#1..#0 CFI-Subchannel Control for logical port #.
4.6.12 Configurable Interface Subchannel Register (CSCR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Note: In CFI-mode 1:
Semiconductor Group
bit 7
SC31
In CFI-mode 2:
In CFI-mode 3:
The subchannel control bits SC#1..SC#0 specify separately for each logical
port the bit positions to be exchanged with the data memory (DM) when a
connection with a channel bandwidth as defined by the CM-code has been
established:
SC#1
0
0
1
1
SC30
H
SC#0
0
1
0
1
SC21
SC21 = SC01; SC20 = SC00; SC31 = SC11; SC30 = SC10
SC31 = SC21 = SC11 = SC01; SC30 = SC20 = SC10 = SC00
SC0x-control ports 0 and 4; SC1x-control ports 1 and 5;
SC2x-control ports 2 and 6; SC3x-control ports 3 and 7
Bit Positions for CFI Subchannels
having a Bandwidth of
64 kBit/s
7..0
7..0
7..0
7..0
SC20
143
SC11
read/write
read/write
32 kBit/s
7..4
3..0
7..4
3..0
Detailed Register Description
SC10
address: 1B
address: 36
SC01
16 kBit/s
7..6
5..4
3..2
1..0
PEB 20550
PEF 20550
bit 0
H
H
SC00
01.96
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