PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 173
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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SOC1,
SOC0
XCS0,
RCS0
RDS
4.7.9
Access in demultiplexed
Access in multiplexed
Reset value: 00
Note: In the clock modes 0,1 and 3 XCS0 and RCS0 has to be set to ’0’.
TXDE
Note: With RDS = 1 the sampling edge is shifted 1/2 clock phase forward. The data is
RIE
Semiconductor Group
bit 7
P-interface mode:
P-interface mode:
SOC1
internally still processed with the falling edge.
Channel Configuration Register 2 (CCR2)
The function of the TSCA/B-pin can be defined programming SOC1,SOC0.
Transmit/receive Clock Shift, bit 0 (only clock mode 2).
Together with the bits XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR) the clock
shift relative to the frame synchronization signal of the transmit (receive) time
slot can be adjusted. A clock shift of 0…7 bits is programmable (clock mode
2 only!).
Transmit Data Enable.
0…the pin TxDA/B is disabled (in the state high impedance).
1…the pin TxDA/B is enabled. Depending on the programming of bit
Receive Data Sampling.
0 : serial data on RXDA/B is sampled at the falling edge of HDCA/B.
1 : serial data on RXDA/B is sampled at the rising edge of HDCA/B.
Receive frame start Enable.
When set, the RFS-interrupt in register EXIR_A/B is enabled.
SOC0
Bus configuration:
00…the TSCA/B output is activated only during the transmission of a
10…the TSCA/B-output is always high (disabled).
11…the TSCA/B-output indicates the reception of a data frame (active
Point-to-point configuration:
0x…the TSCA/B-output is activated during the transmission of a frame.
1x…the TSCA/B-output is activated during the transmission of a frame
CCR1:ODS it has a push pull or open drain characteristic.
H
frame delayed by one clock period. When transmission was
stopped due to a collision TSCA/B remains inactive.
low).
and of inter frame timefill.
XCS0
RCS0
read/write
read/write
173
TXDE
address: (Ch-A/Ch-B): 2C
address: (Ch-A/Ch-B): 58
Detailed Register Description
RDS
RIE
PEB 20550
PEF 20550
H
H
bit 0
/D8
/6C
H
H
0
01.96
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