PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 245
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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W:MACR =
Table 38
Memory Operation Codes for Accesses to the DM Data Field
MOC3 … 0
0000
0001
0011
0010
0111
0110
0101
0100
The Procedure for Writing to the Upstream DM Data Field is
W:MADR = value to be transmitted in the PCM (sub)timeslot
W:MAAR = address of the desired (upstream)
MOC3 … 0 defines the bandwidth and the position of the subchannel according to
table 38.
The Procedure for Reading the DM Data Field is
W:MAAR = address of the desired PCM timeslot encoded according to figure 84
W:MACR = 1000 0000
wait for STAR:MAC = 0
R:MADR = value
Figure 85 illustrates the access to the Data Memory Data Field.
1
2
Semiconductor Group
The U/D bit of MAAR will implicitly be set to 1.
When reading a DM data field location, all 8 bits are read regardless of the bandwidth selected by the MOC
bits.
figure 84
bit 7
0
B
MOC3
= 80
H
Transferred Bits
–
bits 7 … 0
bits 7 … 4
bits 3 … 0
bits 7 … 6
bits 5 … 4
bits 3 … 2
bits 1 … 0
2)
MOC2
245
MOC1
1)
PCM timeslot encoded according to
MOC0
Channel Bandwidth
–
64 kBit/s
32 kBit/s
32 kBit/s
16 kBit/s
16 kBit/s
16 kBit/s
16 kBit/s
0
Application Hints
0
PEB 20550
PEF 20550
bit 0
0
01.96
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