PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 291
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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W:MAAR
W:MACR
W:MADR
W:MAAR
W:MACR
After these programming steps, the ELIC memory will have the following contents:
Figure 102
Control Memory Contents for Central D-Channel Handling
W:MADR
Semiconductor Group
Up-
stream
Down-
stream
CFI
Frame
0
127
0
127
P1, TS10
P1, TS11
P1, TS10
P1, TS11
= 1010 0100
= 1010 1011
= 0111 0101
= 0000 0010
= 1010 0100
= 0110 0000
Code Field
0 1
0
1
1
0
0
1
0
0
1
1
0
0
0
1
Control Memory
B
B
B
B
B
B
0 0 0
1
1
1 1
0
1 1 1 1 1 1 1
Data Field
0
1 0 1 0 1 0
C/I Value
C/I Value
; pointer to PCM port 2, TS8
; upstream odd TS, port 1 timeslot 11
; write CM code + data fields, CM code ‘0101’
; set bits 3 … 2 to low Z and rest of timeslot to high Z
; pointer to PCM port 2, TS8
; write DM CF, single channel tristate command
0
1
0
0
0
0
1
0
1
1
291
Code Field
0 0 1
0
Data Memory
Data Field
Application Hints
Bits 3, 2
Bits 5, 4
P2, TS8
P0, TS5
PEB 20550
PEF 20550
PCM
Frame
0
0
127
127
Up-
stream
Down-
stream
ITD08081
01.96
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