PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 42
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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PEB 20550
PEF 20550
Functional Description
ALE
D 0-7 A 0-7
DS
R/W
CSS CSE
ALE
D 0-7
A 0-7
RD
WR
CSS
CSE
ALE
AD 0-7
RD
WR
CSS
CSE
R
R
ELIC with Siemens/Intel Type
ELIC with Siemens/Intel Type
R
ELIC with Motorola
Interface, Demultiplexed
Interface, Multiplexed
Type Interface
Address/Data Bus
Address/Data Bus
ITD05822
Figure 23
Selectable Bus Interface Structures
In order to simplify the use of 8- and 16-bit Siemens / Intel type CPUs, different register
addresses are defined in multiplexed and demultiplexed bus mode (see chapter 3.1). In
the multiplexed mode even addresses are used (AD0 always 0), if EMODE:DMXAD = 0.
ELIC-data is always transferred in the low data byte.
2.2.2
Parallel Ports
The ELIC provides a 4-bit wide I/O-port. A programmable configuration register
(PCON1) controls whether the individual bits are used as inputs or outputs. The port is
read/written like a on chip register (PORT1).
If port 1 is to be configured as an output, please note that after reset the port is an input.
The PORT1 register thus reflects the state of port 1 before it is configured as an output.
If it is required that port 1 puts out a defined value immediately on being set as output,
large (e.g. > 10 k ) pull-up or pull-down resistors should be applied.
After the port has been configured as output, its value can of course simply be set via
the PORT1-register.
Additionally, when the bus interface is used in multiplexed bus mode (ALE switching),
the pins A0,P0.0 - A7,P0.7 constitute a parallel 8-bit wide input port. The port is read like
an on chip register (PORT0). The current values on the input port is latched with the
falling edge of RD, DS.
Semiconductor Group
42
01.96
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