PEB20571FV31XT Infineon Technologies, PEB20571FV31XT Datasheet - Page 115
PEB20571FV31XT
Manufacturer Part Number
PEB20571FV31XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB20571FV31XT.pdf
(308 pages)
Specifications of PEB20571FV31XT
Lead Free Status / Rohs Status
Compliant
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4.3.2.4
Figure 34
The following description analyses the frame-wise circular-buffering scheme, on a frame
to frame basis.
Assume that during frame n, buffer-0 is used as I-buffer, while buffer-1 is used as D-
buffer. The IOMU stores the incoming frame-n time-slots in buffer-0 input-blocks and
drives outward the frame n time-slots which are read from buffer-0 output-blocks. At the
same time the DSP reads the time-slots that arrived during frame n-1 (the previous
frame) from buffer-1 input-blocks and prepares the time-slots to be driven outward in the
next frame, frame n+1, in buffer-1 output blocks.
Data Sheet
DU1
DU0
DD1
DD0
Circular Buffer Architecture
Serial
IOMU Frame-Wise Circular-Buffer Architecture
DELIC
Serial
IOMU
98
Parallel
Parallel
Functional Description
I-BUFFER
D-BUFFER
Frame-wise
Buffer
Swapping
every frame
DSP
out0
out1
out0
out1
in0
in0
in1
in1
PEB 20570
PEB 20571
Belongs
to the
IOMU
Belongs
to the
DSP
2003-07-31
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