GWIXP460BAD Intel, GWIXP460BAD Datasheet - Page 148

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GWIXP460BAD

Manufacturer Part Number
GWIXP460BAD
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP460BAD

Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Electrical Specifications
Table 70.
Table 71.
May 2005
148
HPI* Timing Symbol Description
HPI*–8 Mode Write Accesses Values
NOTES:
1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
6. One cycle is the period of the Expansion Bus clock.
7. Timing was designed for a system load between 5 pF and 60 pF for high drive setting.
T
T
T
T
Symbol
T
cs2hds1val
hds1_pulse
data_setup
add_setup
data_hold
for the address phase. This setting is required to ensure that in the event of an HRDY, the IXP45X/
IXP46X network processors have had sufficient time to recognize the HRDY and hold the address phase
for at least one clock pulse after the HRDY is de-active.
clocks for setup phase.
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the IXP45X/
IXP46X network processors have had sufficient time to recognize the HRDY and hold the data setup
phase for at least one clock pulse after the HRDY is de-active
Expansion Bus interface.
until HRDY is de-active
State
T
recov
T1
T2
T3
T4
T5
Valid time that address is asserted on the line. The
address is asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data
strobe being active.
Pulse width of the HDS1 data strobe
Data valid prior to the rising edge of the HDS1 data
strobe.
Data valid after the rising edge of the HDS1 data strobe.
Time required between successive accesses on the
expansion interface.
Setup/Chip Select Timing
Recovery Phase
Address Timing
Strobe Timing
Intel
Description
Hold Timing
®
IXP45X and Intel
Parameter
®
IXP46X Product Line of Network Processors Datasheet
Min
3
3
2
3
2
Max
16
17
4
4
4
Min.
11
3
4
4
4
2
Document Number:
Cycles
Cycles
Cycles
Cycles
Cycles
Unit
Max. Units
45
36
17
4
5
5
Cycles 1, 5, 6
Cycles 5, 6
Cycles 2, 4, 5
Cycles 3, 5, 6
Cycles 3, 6
Cycles 4, 6
1, 5, 6
2, 6
3, 5, 6
6
6
Notes
306261-002
Notes

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