GWIXP460BAD Intel, GWIXP460BAD Datasheet - Page 161

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GWIXP460BAD

Manufacturer Part Number
GWIXP460BAD
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP460BAD

Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
5.6.3
Figure 48.
Table 81.
Intel
Document Number:
T
T
T
T
T
T
NOTES:
1. T
2. The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a programmable-logic
RELEASE_PWON_RST_N
RELEASE_RESET_IN_N
PLL_LOCK
EX_ADDR_SETUP
EX_ADDR_HOLD
WARM_RESET
EX_ADDR[24:0]-Pull Up/Down
used the 500-ms delay is not required.
device is used to drive the EX_ADDR signals instead of pull-downs, the signals must be active until PLL_LOCK is active.
®
RELEASE_PWRON_RST_N
IXP45X and Intel
PWRON_RESET_N
Symbol
EX_ADDR[24:0]
RESET_IN_N
PLL_LOCK
V
V
V
CCM
CCP
CC
Reset Timings
Reset Timings
Reset Timings Table Parameters
306261-002
®
IXP46X Product Line of Network Processors Datasheet
Minimum time required to hold the PWON_RST_N at logic
0 state after stable power has been applied to the IXP45X/
IXP46X network processors.
Minimum time required to hold the RESET_IN_N at logic 0
state after PWON_RST_N has been released to a logic 1
state. The RESET_IN_N signal must be held low when the
PWON_RST_N signal is held low.
Maximum time for PLL_LOCK signal to drive to logic 1 after
RESET_IN_N is driven to logic 1 state. The boot sequence
does not occur until this period is complete.
Minimum time for the EX_ADDR signals to drive the inputs
prior to RESET_IN_N being driven to logic 1 state. This is
used for sampling configuration information.
Minimum/maximum time for the EX_ADDR signals to drive
the inputs prior to PLL_LOCK being driven to logic 1 state.
This is used for sampling configuration information.
Minimum time required to drive RESET_IN_N signal to
logic 0 in order to cause a reset after the IXP45X/IXP46X
network processors have been in normal operation. The
power must remain stable and the PWON_RST_N signal
must remain stable.
is the time required for the internal oscillator to reach stability. When an external oscillator is being
T
RELEASE_PWRON_RST_N
Parameter
T
EX_ADDR_SETUP
CFG Settings To Be Captured
CFG Settings To Be Captured
T
RELEASE_RST_N
T
Min.
500
500
PLL_LOCK
10
50
0
Typ.
Electrical Specifications
T
EX_ADDR_HOLD
IXP46X Drives Outputs
Max.
10
20
Units
ms
ns
µs
ns
ns
ns
May 2005
Note
1
2
2
161

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